Semiconductor device and method for manufacturing the same

ABSTRACT

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, there occurs a problem that it is difficult to mount an IC chip including a driver circuit for driving the gate and signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. The pixel portion and the driver portion are provided over the same substrate, whereby manufacturing cost can be reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the semiconductor device.

2. Description of the Related Art

A thin film transistor formed over a flat plate such as a glass substrate is manufactured using amorphous silicon or polycrystalline silicon, as typically seen in a liquid crystal display device. A thin film transistor manufactured using amorphous silicon has low field effect mobility, but such a transistor can be formed over a glass substrate with a larger area. On the other hand, a thin film transistor manufactured using polycrystalline silicon has high field effect mobility, but a crystallization step such as laser annealing is necessary and such a transistor is not always suitable for a larger glass substrate.

In view of the foregoing, attention has been drawn to a technique by which a thin film transistor is manufactured using an oxide semiconductor, and such a transistor is applied to an electronic device or an optical device. For example, Patent Document 1 and Patent Document 2 disclose a technique by which a thin film transistor is manufactured using zinc oxide or an In—Ga—Zn—O-based oxide semiconductor as an oxide semiconductor film and such a transistor is used as a switching element or the like of an image display device.

[Reference]

[Patent Document 1] Japanese Published Patent Application No. 2007-123861

[Patent Document 2] Japanese Published Patent Application No. 2007-096055

SUMMARY OF THE INVENTION

The field effect mobility of a thin film transistor in which a channel formation region is provided in an oxide semiconductor is higher than that of a thin film transistor using amorphous silicon. The oxide semiconductor film can be formed by a puttering method or the like at a temperature of 300° C. or lower. Its manufacturing process is easier than that of a thin film transistor using polycrystalline silicon.

Such an oxide semiconductor is expected to be used for forming a thin film transistor over a glass substrate, a plastic substrate, or the like, and to be applied to a display device such as a liquid crystal display device, an electroluminescent display device, or electronic paper.

When the size of a display region of a display device is increased, the number of pixels is increased and thus the number of gate lines and signal lines is increased.

In addition, as a display device has a higher definition, the number of pixels is increased and thus the number of gate lines and signal lines is increased. When the number of the gate lines and the signal lines is increased, it is difficult to mount an IC chip including a driver circuit for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased.

Therefore, it is an object to reduce manufacturing cost by employing a thin film transistor using an oxide semiconductor in at least part of a driver circuit for driving a pixel portion.

In the case of employing a thin film transistor using an oxide semiconductor in at least part of a driver circuit for driving a pixel portion, high dynamic characteristics (on characteristics or frequency characteristics (referred to as f characteristics)) are required for the thin film transistor. It is another object to provide a thin film transistor having high dynamic characteristics (on characteristics) and to provide a driver circuit which enables high-speed operation.

In addition, it is an object of an embodiment of the present invention to provide a semiconductor device provided with a highly reliable thin film transistor in which an oxide semiconductor layer is used for a channel.

Gate electrodes are provided above and below an oxide semiconductor layer to realize improvement of on characteristics and reliability of a thin film transistor.

Further, by controlling gate voltage applied to the upper and lower gate electrodes, threshold voltage can be controlled. The upper and lower gate electrodes may be electrically connected to each other so as to have the same potential, or the upper and lower gate electrodes may be connected to different wirings so as to have different potentials. For example, when the threshold voltage is set at 0 or close to 0 to reduce driving voltage, reduction of power consumption can be achieved. Alternatively, when the threshold voltage is set positive, the thin film transistor can function as an enhancement type transistor. Further alternatively, when the threshold voltage is set negative, the thin film transistor can function as a depletion type transistor.

For example, an inverter circuit including a combination of the enhancement type transistor and the depletion type transistor (hereinafter, referred to as an EDMOS circuit) can be used for a driver circuit. The driver circuit includes at least a logic circuit portion, and a switch portion or a buffer portion. The logic circuit portion has a circuit structure including the above EDMOS circuit. Further, a thin film transistor in which large on current can flow is preferably used for the switch portion or the buffer portion. A depletion type transistor or a thin film transistor including gate electrodes above and below an oxide semiconductor layer is used.

Thin film transistors having different structures can be manufactured over the same substrate without greatly increasing the number of steps. For example, the EDMOS circuit using the thin film transistor including gate electrodes above and below the oxide semiconductor layer may be formed in the driver circuit for high-speed driving, and a thin film transistor including a gate electrode only below the oxide semiconductor layer may be used for a pixel portion.

Note that an n-channel TFT whose threshold voltage is positive is referred to as an enhancement type transistor, and an n-channel TFT whose threshold voltage is negative is referred to as a depletion type transistor throughout this specification.

Examples of a material for the gate electrode provided above the oxide semiconductor layer include an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), and an alloy containing any of the above elements as its component, and any conductive film can be used without particular limitation.

Further, the gate electrode is not limited to a single layer structure containing any of the above elements, and can have a stacked structure of two or more layers.

As a material for the gate electrode provided above the oxide semiconductor layer, the same material (such as a transparent conductive film in the case of a transmissive display device) as that of a pixel electrode can be used. For example, the gate electrode provided above the oxide semiconductor layer can be formed in the same step as a step for forming the pixel electrode which is electrically connected to the thin film transistor in the pixel portion. Consequently, the thin film transistor provided with the gate electrodes above and below the oxide semiconductor layer can be formed without greatly increasing the number of steps. In addition, the gate electrode is provided above the oxide semiconductor layer, whereby in a bias-temperature stress test (hereinafter, referred to as a BT test) for examining reliability of a thin film transistor, the amount of change in threshold voltage of the thin film transistor between before and after the BT test can be reduced. That is, the gate electrode is provided above the oxide semiconductor layer, whereby reliability can be improved.

One embodiment of the invention disclosed in this specification is a semiconductor device comprising a first gate electrode over an insulating surface; a first insulating layer over the first gate electrode; a source electrode and a drain electrode over the first insulating layer; an oxide semiconductor layer over the source electrode and the drain electrode; a second insulating layer covering the oxide semiconductor layer; and a second gate electrode over the second insulating layer, wherein the oxide semiconductor layer is formed over the first insulating layer and overlaps with the first gate electrode, at least part of the oxide semiconductor layer is provided between the source electrode and the drain electrode, and the second gate electrode overlaps with the oxide semiconductor layer and the first gate electrode.

With the above structure, at least one of the above objects is achieved.

In the above structure, a width of the second gate electrode is made larger than a width of the first gate electrode, whereby voltage can be applied to the whole oxide semiconductor layer from the second gate electrode.

Alternatively, in the above structure, when a width of the first gate electrode is smaller than a width of the second gate electrode, an area of the first gate electrode which overlaps with the source electrode and the drain electrode is reduced, so that parasitic capacitance can be reduced. Further alternatively, a structure in which a width of the second gate electrode is made smaller than a distance between the source electrode and the drain electrode so that the second gate electrode does not overlap with the source electrode and the drain electrode, thereby further reducing the parasitic capacitance may be employed.

Further, a manufacturing method of the above structure has a feature. The manufacturing method is a method for manufacturing a semiconductor device, comprising the steps of forming a first gate electrode over an insulating surface; forming a first insulating layer over the first gate electrode; forming a source electrode and a drain electrode over the first insulating layer; performing plasma treatment on the first insulating layer, the source electrode, and the drain electrode; forming an oxide semiconductor layer over the source electrode and the drain electrode; forming a second insulating layer covering the oxide semiconductor layer; and forming a second gate electrode over the second insulating layer. In this manufacturing method, the second gate electrode is formed of the same material and the same mask as a pixel electrode, whereby the semiconductor device can be manufactured without greatly increasing the number of steps.

Another embodiment of the invention is a semiconductor device comprising a pixel portion and a driver circuit, wherein the pixel portion includes at least a first thin film transistor having a first oxide semiconductor layer, the driver circuit includes at least an EDMOS circuit in which a second thin film transistor having a second oxide semiconductor layer and a third thin film transistor having a third oxide semiconductor layer are included, the third thin film transistor includes a first gate electrode below the third oxide semiconductor layer and a second gate electrode above the third oxide semiconductor layer, and at least part of the third oxide semiconductor layer is provided between a source electrode and a drain electrode, and the second gate electrode overlaps with the third oxide semiconductor layer and the first gate electrode.

In the above structure, when the first thin film transistor in the pixel portion is electrically connected to a pixel electrode and the pixel electrode is formed of the same material as the second gate electrode in the driver circuit, the semiconductor device can be manufactured without increasing the number of steps.

In the above structure, when the first thin film transistor in the pixel portion is electrically connected to a pixel electrode and the pixel electrode is formed of a material different from the second gate electrode in the driver circuit, for example, when the pixel electrode is a transparent conductive film and the second gate electrode is an aluminum film, resistance of the second gate electrode in the driver circuit can be reduced.

Further, a so-called dual-gate structure is provided, in which the third oxide semiconductor layer in the driver circuit overlaps with the first gate electrode with the first insulating layer interposed therebetween and also overlaps with the second gate electrode with the second insulating layer interposed therebetween.

As a semiconductor device having a driver circuit, besides a liquid crystal display device, a light-emitting display device using a light-emitting element and a display device using an electrophoretic display element which is also referred to as electronic paper can be given.

Note that a “display device” in this specification means an image display device, a light-emitting device, or a light source (including a lighting device). Further, the display device includes any of the following modules in its category: a module including a connector such as an flexible printed circuit (FPC), a tape automated bonding (TAB) tape, or a tape carrier package (TCP); a module having a TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element by a chip on glass (COG) method.

In a light-emitting display device using a light-emitting element, a plurality of thin film transistors are included in a pixel portion, and a portion in which a gate electrode of a thin film transistor is electrically connected to a source wiring or a drain wiring of another transistor is included in the pixel portion.

Since a thin film transistor is easily broken due to static electricity or the like, a protective circuit for protecting a driver circuit is preferably provided over the same substrate for a gate line or a source line. The protective circuit is preferably formed using a non-linear element including an oxide semiconductor.

The oxide semiconductor used in this specification is a thin film expressed by InMO₃(ZnO)_(m) (m>0), and a thin film transistor using the thin film as a semiconductor layer is manufactured. Note that M denotes one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, M is Ga in some cases; meanwhile, M contains the above metal element such as Ni or Fe in addition to Ga (Ga and Ni or Ga and Fe) in other cases. Further, the above oxide semiconductor may contain Fe or Ni, another transitional metal element, or an oxide of the transitional metal as an impurity element in addition to the metal element contained as M. In this specification, this thin film is also referred to as an In—Ga—Zn—O-based non-single-crystal film.

After the In—Ga—Zn—O-based non-single-crystal film is formed by a sputtering method, it is heated at 200° C. to 500° C., typically 300° C. to 400° C., for 10 to 100 minutes. Note that an amorphous structure is observed in the In—Ga—Zn—O-based non-single-crystal film analyzed by XRD analysis.

An oxide semiconductor typified by the In—Ga—Zn—O-based non-single-crystal film is a material having a wide energy gap (Eg); therefore, even if two gate electrodes are provided above and below an oxide semiconductor layer, increase of off current can be suppressed.

Note that the ordinal numbers such as “first” and “second” in this specification are used for convenience and do not denote the order of steps and the stacking order of layers. In addition, the ordinal numbers in this specification do not denote particular names which specify the present invention.

By forming the thin film transistor using the oxide semiconductor interposed between the two gate electrodes provided above and below the oxide semiconductor in a peripheral circuit such as a gate line driver circuit or a source line driver circuit, or a pixel portion, manufacturing cost is reduced.

With the thin film transistor using the oxide semiconductor interposed between the two gate electrodes provided above and below the oxide semiconductor, in a BT test, the amount of change in threshold voltage of the thin film transistor between before and after the BT test can be reduced. That is, the thin film transistor includes the oxide semiconductor interposed between the two gate electrodes provided above and below the oxide semiconductor, whereby reliability of the thin film transistor can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A, 1B, and 1C are cross-sectional views illustrating an example of a display device of Embodiment 1, another example of a display device of Embodiment 1, and another example of a display device of Embodiment 1, respectively.

FIGS. 2A, 2B, and 2C are a cross-sectional view, an equivalent circuit diagram, and a top view of a semiconductor device of Embodiment 2, respectively.

FIGS. 3A and 3B are block diagrams illustrating a whole display device of Embodiment 3.

FIG. 4 is a diagram illustrating arrangement of a wiring, an input terminal, and the like in a display device of Embodiment 3.

FIG. 5 is a block diagram illustrating a structure of a shift register circuit.

FIG. 6 is a diagram illustrating an example of a flip-flop circuit.

FIG. 7 is a view illustrating a layout view (a top view) of a flip-flop circuit.

FIG. 8 is a diagram illustrating a timing chart for showing operation of a shift register circuit.

FIGS. 9A to 9C are views illustrating a method for manufacturing a semiconductor device of Embodiment 4.

FIGS. 10A to 10C are views illustrating a method for manufacturing a semiconductor device of Embodiment 4.

FIG. 11 is a view illustrating a method for manufacturing a semiconductor device of Embodiment 4.

FIG. 12 is a view illustrating a method for manufacturing a semiconductor device of Embodiment 4.

FIG. 13 is a view illustrating a method for manufacturing a semiconductor device of Embodiment 4.

FIG. 14 is a view illustrating a semiconductor device of Embodiment 4.

FIGS. 15A1, 15A2, 15B1, and 15B2 are views illustrating semiconductor devices of Embodiment 4.

FIG. 16 is a view illustrating a semiconductor device of Embodiment 4.

FIG. 17 is a cross-sectional view illustrating a semiconductor device of Embodiment 5.

FIG. 18 is a diagram illustrating a pixel equivalent circuit of a semiconductor device of Embodiment 6.

FIGS. 19A to 19C are cross-sectional views illustrating semiconductor devices of Embodiment 6.

FIGS. 20A and 20B are a top view and a cross-sectional view illustrating a semiconductor device of Embodiment 6, respectively.

FIGS. 21A1 and 21A2 are top views and FIG. 21B is a cross-sectional view illustrating a semiconductor device of Embodiment 7.

FIG. 22 is a cross-sectional view illustrating a semiconductor device of Embodiment 7.

FIGS. 23A to 23D are external views illustrating examples of electronic devices.

FIGS. 24A and 24B are external views illustrating examples of a television device and a digital photo frame, respectively.

FIGS. 25A and 25B are external views illustrating examples of cellular phones.

FIG. 26 is a cross-sectional view illustrating a semiconductor device of Embodiment 9.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments will be described below with reference to the accompanying drawings. Note that the invention to be disclosed in this specification is not limited to the description of the embodiments given below, and it is obvious to those skilled in the art that the modes and details can be modified in various ways without departing from the spirit of the invention. Therefore, the present invention should not be interpreted as being limited to description in the embodiments below.

Embodiment 1

FIG. 1A illustrates an example in which a first thin film transistor 430 used for a driver circuit and a second thin film transistor 170 used for a pixel portion are provided over the same substrate. Note that FIG. 1A illustrates an example of a cross-sectional view of a display device.

The pixel portion and the driver circuit are formed over the same substrate. In the pixel portion, the second thin film transistors 170 which are enhancement type transistors arranged in a matrix form are each used for switching on/off of voltage application to a pixel electrode 110. The second thin film transistor 170 arranged in the pixel portion is formed using an oxide semiconductor layer 103. As for electric characteristics of the second thin film transistor, on/off ratio is 10⁹ or more at a gate voltage of ±20 V; therefore, display contrast can be improved, and further, leakage current is small, whereby low-power-consumption driving can be realized. The on/off ratio is a ratio of on current to off current (I_(on)/I_(off)), and the higher the value of the I_(on)/I_(off) is, the better switching characteristics is. Thus, high on/off ratio contributes to improvement of display contrast. Note that on current is current which flows between a source electrode and a drain electrode when a transistor is in an on state. Meanwhile, off current is current which flows between the source electrode and the drain electrode when the transistor is in an off state. For example, in an n-channel transistor, the off current is current which flows between a source electrode and a drain electrode when gate voltage is lower than threshold voltage of the transistor. Therefore, an enhancement type transistor is preferably used for the pixel portion to achieve high contrast and low-power-consumption driving.

In the driver circuit, at least one thin film transistor 430 including a first gate electrode 401 below an oxide semiconductor layer 405 and a second gate electrode 470 above the oxide semiconductor layer 405 is used. The second gate electrode 470 can also be called a back-gate electrode. By forming the back-gate electrode, in a bias-temperature stress test (hereinafter, referred to as a BT test) for examining reliability of a thin film transistor, the amount of change in threshold voltage of the thin film transistor between before and after the BT test can be reduced.

A structure of the thin film transistor 430 is described with reference to FIG. 1A. The first gate electrode 401 provided over a substrate 400 having an insulating surface is covered with a first gate insulating layer 403. A first wiring 409 and a second wiring 410 are provided over the first gate insulating layer 403 overlapping with the first gate electrode 401. The oxide semiconductor layer 405 is provided over the first wiring 409 and the second wiring 410 which function as a source electrode and a drain electrode. A second gate insulating layer 412 is provided so as to cover the oxide semiconductor layer 405. Further, the second gate electrode 470 is provided over the second gate insulating layer 412.

Further, the first gate electrode 401 and the second gate electrode 470 may be electrically connected to each other so as to have the same potential. When the first gate electrode 401 and the second gate electrode 470 have the same potential, gate voltage can be applied from upper and lower sides of the oxide semiconductor layer, so that the amount of current which flows in an on state can be increased.

Further, when a control signal line for shifting the threshold voltage to a negative value is electrically connected to either the first gate electrode 401 or the second gate electrode 470, a depletion type TFT can be formed.

Alternatively, when a control signal line for shifting the threshold voltage to a positive value is electrically connected to either the first gate electrode 401 or the second gate electrode 470, an enhancement type TFT can be formed.

Further, there is no particular limitation on a combination of two thin film transistors used for the driver circuit, and a combination of a thin film transistor including one gate electrode as the depletion type TFT and a thin film transistor including two gate electrodes as the enhancement type TFT may be employed. In that case, a thin film transistor in the pixel portion has a structure in which gate electrodes are provided above and below the oxide semiconductor layer.

Alternatively, the thin film transistor in the pixel portion may have a structure in which gate electrodes are provided above and below the oxide semiconductor layer, and the enhancement type TFT and the depletion type TFT in the driver circuit may each have a structure in which gate electrodes are provided above and below the oxide semiconductor layer. In that case, a structure in which a control signal line for controlling the threshold voltage is electrically connected to either of the upper and lower gate electrodes and the connected gate electrode controls the threshold voltage is employed.

Note that in FIG. 1A, the second gate electrode 470 is formed of the same material as the pixel electrode 110 in the pixel portion, for example, using a transparent conductive film in the case of a transmissive liquid crystal display device, in order to reduce the number of steps. However, there is no particular limitation on the second gate electrode 470. In addition, an example in which a width of the second gate electrode 470 is larger than a width of the first gate electrode 401 and also larger than a width of the oxide semiconductor layer is illustrated; however, there is no particular limitation on the width of the second gate electrode 470.

FIG. 1B illustrates an example different from FIG. 1A in the material and the width of the second gate electrode. Further, FIG. 1B illustrates an example of a display device in which the thin film transistor 170 connected to an organic light-emitting element or an inorganic light-emitting element is included in the pixel portion.

In FIG. 1B, as a material for an electrode 471 which functions as a second gate electrode of a thin film transistor 432, a metal material (an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), or an alloy containing any of the above-described elements as its component) is used. A width of the electrode 471 in a cross section is smaller than that of the second gate electrode 470 in FIG. 1A.

Further, the width of the electrode 471 is smaller than a width of the oxide semiconductor layer. By reducing the width of the electrode 471, the overlapping area of the electrode 471 with the first wiring 409 and the second wiring 410 with the second gate insulating layer 412 interposed therebetween can be reduced, so that parasitic capacitance can be reduced.

The light-emitting element includes at least a first electrode 472, a light-emitting layer 475, and a second electrode 474. In FIG. 1B, the electrode 471 is formed of the same material as the first electrode 472 in the pixel portion, for example, using aluminum or the like, in order to reduce the number of steps; however, there is no particular limitation on the electrode 471. Further, in FIG. 1B, an insulating layer 473 functions as a partition wall for insulating the first electrodes of the adjacent pixels from each other.

Further, FIG. 1C illustrates an example different from FIG. 1A in the material and the width of the second gate electrode. In FIG. 1C, as a material for an electrode 476 which functions as a second gate electrode of a thin film transistor 433, a metal material (an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), or an alloy containing any of the above-described elements as its component) is used. A width of the second gate electrode in the cross section is smaller than that in FIG. 1B. When the width is still smaller than that in FIG. 1B, it is possible to form the second gate electrode so as not to overlap with the first wiring 409 and the second wiring 410 with the second gate insulating layer 412 interposed therebetween, and thus the parasitic capacitance can further be reduced. A width of the electrode 476 illustrated in FIG. 1C is smaller than a distance between the first wiring 409 and the second wiring 410. In the case of forming the electrode 476 having such a small width, a process using wet etching or the like is preferably performed so that both ends of the electrode 476 are positioned inner than end portions of a resist mask. However, in FIG. 1C, since a metal material different from that of the pixel electrode 110 is used, one more photolithography step for forming the electrode 476 is added, and one more mask is needed.

When the thin film transistor including the oxide semiconductor interposed between the two gate electrodes provided above and below the oxide semiconductor is used for a peripheral circuit such as a gate line driver circuit or a source line driver circuit, or a pixel portion, which is used for a liquid crystal display device, a light-emitting display device, or electronic paper, high speed driving or low power consumption can be achieved. Further, both the pixel portion and the driver circuit can be provided over the same substrate without greatly increasing the number of steps. By providing various circuits in addition to the pixel portion over the same substrate, manufacturing cost of a display device can be reduced.

Embodiment 2

One thin film transistor has been described as the thin film transistor in the driver circuit in Embodiment 1; however, in Embodiment 2, an example of forming an inverter circuit of a driver circuit with the use of two n-channel thin film transistors will be described below. A thin film transistor illustrated in FIG. 2A is the same as the thin film transistor 430 illustrated in FIG. 1A of Embodiment 1; therefore, the same parts are denoted by the same reference numerals.

The driver circuit for driving a pixel portion is formed using an inverter circuit, a capacitor, a resistor, and the like. In the case where the inverter circuit is formed using two n-channel TFTs in combination, there are an inverter circuit having a combination of an enhancement type transistor and a depletion type transistor (hereinafter, referred to as an EDMOS circuit) and an inverter circuit having a combination of two enhancement type TFTs (hereinafter, referred to as an EEMOS circuit).

A cross-sectional structure of the inverter circuit of the driver circuit is illustrated in FIG. 2A. Note that the thin film transistor 430 and a second thin film transistor 431 illustrated in FIG. 2A to 2C are bottom-gate thin film transistors, and are examples of thin film transistors in which a wiring is provided under a semiconductor layer.

In FIG. 2A, the first gate electrode 401 and a gate electrode 402 are provided over the substrate 400. The first gate electrode 401 and the gate electrode 402 can be formed to have a single-layer structure or a stacked structure using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium or an alloy material containing any of these as its main component.

As a two-layer stacked structure of the first gate electrode 401 and the gate electrode 402, for example, a two-layer stacked structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked is preferable. As a three-layer stacked structure, stacked layers of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer is preferable.

Further, the first wiring 409 and the second wiring 410 are provided over the first gate insulating layer 403 which covers the first gate electrode 401 and the gate electrode 402. The second wiring 410 is directly connected to the gate electrode 402 through a contact hole 404 formed in the first gate insulating layer 403.

The oxide semiconductor layer 405 is provided over the first wiring 409 and the second wiring 410. Further, a second oxide semiconductor layer 407 is provided over a third wiring 411.

The thin film transistor 430 includes the first gate electrode 401 and the oxide semiconductor layer 405 overlapping with the first gate electrode 401 with the first gate insulating layer 403 interposed therebetween. The first wiring 409 is a power supply line to which negative voltage VDL is applied (a negative power supply line). This power supply line may be a power supply line with a ground potential (a ground potential power supply line).

Further, the second thin film transistor 431 includes the gate electrode 402 and the second oxide semiconductor layer 407 overlapping with the gate electrode 402 with the first gate insulating layer 403 interposed therebetween. The third wiring 411 is a power supply line to which positive voltage VDH is applied (a positive power supply line).

Further, a top view of the inverter circuit of the driver circuit is illustrated in FIG. 2C. In FIG. 2C, a cross-section taken along a chain line Z1-Z2 corresponds to FIG. 2A.

Further, an equivalent circuit of the EDMOS circuit is illustrated in FIG. 2B. A circuit connection illustrated in FIG. 2A corresponds to that in FIG. 2B, and is an example in which the thin film transistor 430 is an enhancement type n-channel transistor while the second thin film transistor 431 is a depletion type n-channel transistor.

In this embodiment, in order to make the thin film transistor 430 an enhancement type n-channel transistor, the second gate insulating layer 412 is provided over the oxide semiconductor layer 405 and the second gate electrode 470 is provided over the second gate insulating layer 412 so that threshold value of the thin film transistor 430 is controlled by voltage applied to the second gate electrode 470.

Further, the second gate insulating layer 412 also functions as a protective layer covering the second oxide semiconductor layer 407.

Note that an example in which the second wiring 410 is directly connected to the gate electrode 402 through the contact hole 404 formed in the first gate insulating layer 403 is illustrated in FIGS. 2A and 2C; however, a connection electrode may be separately provided, thereby electrically connecting the second wiring 410 and the gate electrode 402 without being particularly limited to the above example.

Further, this embodiment can be freely combined with Embodiment 1.

Embodiment 3

In this embodiment, a display device will be described with reference to block diagrams and the like.

FIG. 3A illustrates an example of a block diagram of an active matrix liquid crystal display device. The liquid crystal display device illustrated in FIG. 3A includes, over a substrate 300, a pixel portion 301 having a plurality of pixels each provided with a display element; a scan line driver circuit 302 which controls a scan line connected to a gate electrode of each pixel; and a signal line driver circuit 303 which controls video signal input to a selected pixel.

FIG. 3B illustrates an example of a block diagram of an active matrix light-emitting display device. The light-emitting display device illustrated in FIG. 3B includes, over a substrate 310, a pixel portion 311 having a plurality of pixels each provided with a display element; a first scan line driver circuit 312 and a second scan line driver circuit 313, each of which controls a scan line connected to a gate electrode of a pixel; and a signal line driver circuit 314 which controls video signal input to a selected pixel. In the case where two TFTs (thin film transistor) of a switching TFT and a current controlling TFT are arranged in one pixel, in the light-emitting display device illustrated in FIG. 3B, a signal which is input to a first scan line connected to a gate electrode of the switching TFT is generated in the first scan line driver circuit 312, and a signal which is input to a second scan line connected to a gate electrode of the current controlling TFT is generated in the second scan line driver circuit 313. Note that a structure in which the signal input to the first scan line and the signal input to the second scan line are generated in one scan line driver circuit may also be employed. Alternatively, for example, a plurality of the first scan lines used for controlling operation of a switching element may be provided in each pixel, depending on the number of TFTs included in the switching element. In this case, all signals which are input to the plurality of the first scan lines may be generated in one scan line driver circuit, or signals may be generated separately by a plurality of scan line driver circuits.

Note that modes in which the scan line driver circuit 302, the first scan line driver circuit 312, the second scan line driver circuit 313, and the signal line driver circuits 303 and 314 are manufactured in the display devices are described here; however, part of the scan line driver circuit 302, the first scan line driver circuit 312, or the second scan line driver circuit 313 may be mounted using a semiconductor device such as an IC. Alternatively, part of the signal line driver circuits 303 or 314 may be mounted using a semiconductor device such as an IC.

FIG. 4 is a diagram illustrating a positional relation between a pixel portion and a protective circuit including a signal input terminal 321, a scan line, a signal line, and a non-linear element, which constitute the display device. A pixel portion 327 includes scan lines 323 and signal lines 324 which are arranged over a substrate 320 having an insulating surface so as to intersect with each other. Note that the pixel portion 327 corresponds to the pixel portion 301 and the pixel portion 311 illustrated in FIG. 3A and 3B.

The pixel portion 301 is connected to the signal line driver circuit 303 by a plurality of signal lines Si to Sm (not shown) which are arranged in columns and extended from the signal line driver circuit 303, and connected to the scan line driver circuit 302 by a plurality of scan lines G1 to Gn (not shown) which are arranged in rows and extended from the scan line driver circuit 302. The pixel portion 301 includes a plurality of pixels (not shown) arranged in a matrix form by the signal lines S1 to Sm and the scan lines G1 to Gn. Then, each pixel is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scan line Gi (any one of the scan lines G1 to Gn).

The pixel portion 327 includes a plurality of pixels 328 arranged in a matrix form. The pixel 328 includes a pixel TFT 329 connected to the scan line 323 and the signal line 324, a storage capacitor 330, and a pixel electrode 331.

The pixel structure here illustrates a case where one electrode of the storage capacitor 330 is connected to the pixel TFT 329 and the other electrode thereof is connected to a capacitor line 332. Further, the pixel electrode 331 serves as one electrode which drives a display element (a liquid crystal element, a light-emitting element, a contrast medium (electronic ink), or the like). The other electrode of such a display element is connected to a common terminal 333.

Some protective circuits are provided between the pixel portion 327 and signal line input terminals 322. In addition, other protective circuits are provided between the scan line driver circuit and the pixel portion 327. In this embodiment, a plurality of protective circuits are provided so that the pixel TFT 329 and the like are not broken when surge voltage due to static electricity or the like is applied to the scan line 323, the signal line 324, and a capacitor bus line 337. Therefore, the protective circuits are formed so that charge is released into a common wiring when the surge voltage is applied.

In this embodiment, an example in which a protective circuit 334, a protective circuit 335, and a protective circuit 336 are arranged on a scan line 323 side, on a signal line 324 side, and on a capacitor bus line 337 side, respectively is illustrated. Note that an arrangement position of the protective circuits is not limited thereto. In addition, in a case where the scan line driver circuit is not mounted using a semiconductor device such as an IC, the protective circuit 334 is not necessarily provided on the scan line 323 side.

By use of the TFT described in Embodiment 1 or Embodiment 2 for each of these circuits, the following advantages can be obtained.

A driver circuit is roughly divided into a logic circuit portion, and a switch portion or a buffer portion. A TFT provided in the logic circuit portion preferably has a structure in which threshold voltage can be controlled. On the other hand, a TFT provided in the switch portion or the buffer portion preferably has large on current. By provision of a driver circuit including the TFT described in Embodiment 1 or Embodiment 2, the threshold voltage of the TFT provided in the logic circuit portion can be controlled, and the on current of the TFT provided in the switch portion or the buffer portion can be increased. Furthermore, the TFT described in Embodiment 1 or Embodiment 2 contributes to reducing an area occupied by the driver circuit and narrowing a frame.

A shift register circuit included in the scan line driver circuit is described below.

A shift register circuit illustrated in FIG. 5 includes a plurality of flip-flop circuits 351, a control signal line 352, a control signal line 353, a control signal line 354, a control signal line 355, a control signal line 356, and a reset line 357.

As illustrated in the shift register circuit of FIG. 5, in the flip-flop circuits 351, a start pulse SSP is input to an input terminal IN of the first stage through the control signal line 352, and an output signal terminal S_(out) of the flip-flop circuit 351 of the preceding stage is connected to an input terminal IN of the next stage. Further, a reset terminal RES of the N-th stage (N is a natural number) is connected to an output signal terminal S_(out) of the flip-flop circuit of the (N+3)th stage through the reset line 357. When it is assumed that a first clock signal CLK1 is input to a clock terminal CLK of the flip-flop circuit 351 of the N-th stage through the control signal line 353, a second clock signal CLK2 is input to the clock terminal CLK of the flip-flop circuit 351 of the (N+1)th stage through the control signal line 354. A third clock signal CLK3 is input to the clock terminal CLK of the flip-flop circuit 351 of the (N+2)th stage through the control signal line 355. A fourth clock signal CLK4 is input to the clock terminal CLK of the flip-flop circuit 351 of the (N+3)th stage through the control signal line 356. Then, the first clock signal CLK1 is input to the clock terminal CLK of the flip-flop circuit 351 of the (N+4)th stage through the control signal line 353. In addition, the flip-flop circuit 351 of the N-th stage outputs an output SR_(out)N of the flip-flop circuit of the N-th stage from a gate output terminal G_(out).

Note that connection between the flip-flop circuits 351, and a power source and a power supply line is not illustrated; however, each flip-flop circuit 351 is supplied with a power supply potential Vdd and a power supply potential GND through the power supply line.

Note that the power supply potential described in this specification corresponds to a potential difference in the case where a reference potential is 0 V. Therefore, the power supply potential is also referred to as power supply voltage, or the power supply voltage is referred to as the power supply potential in some cases.

Note that in this specification, description that “A and B are connected to each other” includes the case where A and B are electrically connected to each other in addition to the case where A and B are directly connected to each other. Here, the description that “A and B are electrically connected to each other” expresses the following situation: when an object having any electrical function exists between A and B, A and B have substantially the same potential through the object. Specifically, the description that “A and B are electrically connected to each other” expresses the case where A and B can be regarded to have the same potential in consideration of the circuit operation, such as a case where A and B are connected through a switching element such as a TFT and A and B have substantially the same potential by the conduction of the switching element, or a case where A and B are connected through a resistor and a potential difference generated between the both ends of the resistor does not affect operation of a circuit including A and B.

Next, FIG. 6 illustrates one mode of the flip-flop circuit 351 included in the shift register circuit illustrated in FIG. 5. The flip-flop circuit 351 illustrated in FIG. 6 includes a logic circuit portion 361 and a switch portion 362. The logic circuit portion 361 includes TFTs 363 to 368. Further, the switch portion 362 includes TFTs 369 to 372. Note that a logic circuit portion is a circuit for switching a signal that is output to a switch portion, which is a circuit in the next stage, in response to a signal that is input from an external portion. In addition, a switch portion is a circuit for switching on/off of a TFT which functions as a switch in response to a signal input from an external portion and a control circuit portion, and for outputting current depending on the size and the structure of the TFT.

In the flip-flop circuit 351, an input terminal in is connected to a gate terminal of the TFT 364 and a gate terminal of the TFT 367. A reset terminal RES is connected to a gate terminal of the TFT 363. A clock terminal CLK is connected to a first terminal of the TFT 369 and a first terminal of the TFT 371. A power supply line through which the power supply potential Vdd is supplied is connected to a first terminal of the TFT 364, and a gate terminal and a second terminal of the TFT 366. A power supply line through which the power supply potential GND is supplied is connected to a second terminal of the TFT 363, a second terminal of the TFT 365, a second terminal of the TFT 367, a second terminal of the TFT 368, a second terminal of the TFT 370, and a second terminal of the TFT 372. Further, a first terminal of the

TFT 363, a second terminal of the TFT 364, a first terminal of the TFT 365, a gate terminal of the TFT 368, a gate terminal of the TFT 369, and a gate terminal of the TFT 371 are connected to each other. A first terminal of the TFT 366 is connected to a gate terminal of the TFT 365, a first terminal of the TFT 367, a first terminal of the TFT 368, a gate terminal of the TFT 370, and a gate terminal of the TFT 372. In addition, a gate output terminal G_(out) is connected to a second terminal of the TFT 369 and a first terminal of the TFT 370. An output signal terminal S_(out) is connected to a second terminal of the TFT 371 and a first terminal of the TFT 372.

Note that a case where the TFTs 363 to 372 are all n-channel TFTs is described here.

Note that a TFT is an element having at least three terminals of a gate, a drain, and a source, and has a channel formation region between a drain region and a source region. Current can flow through the drain region, the channel formation region, and the source region. Here, the source and the drain may be exchanged with each other in some cases depending on a structure, operation conditions of the TFT, or the like; therefore, it is difficult to determine which the source is or which the drain is. Therefore, regions functioning as the source and the drain are not referred to as a source and a drain but referred to, for example, as a first terminal and a second terminal, respectively, in some cases. In this case, a terminal functioning as a gate is referred to as a gate terminal.

Next, FIG. 7 illustrates an example of a layout view of the flip-flop circuit 351 illustrated in FIG. 6.

The flip-flop circuit of FIG. 7 includes a power supply line 381 through which the power supply potential Vdd is supplied, a reset line 382, the control signal line 353, the control signal line 354, the control signal line 355, the control signal line 356, a control signal line 383, a power supply line 384 through which the power supply potential GND is supplied, the logic circuit portion 361, and the switch portion 362. The logic circuit portion 361 includes the TFTs 363 to 368. The switch portion 362 includes the TFTs 369 to 372. In FIG. 7, a wiring connected to the gate output terminal G_(out) and a wiring connected to the output signal terminal S_(out) are also illustrated.

FIG. 7 illustrates a semiconductor layer 385, a first wiring layer 386, a second wiring layer 387, a third wiring layer 388, and a contact hole 389. Note that the first wiring layer 386 may be formed of a layer of a gate electrode, the second wiring layer 387 may be formed of a layer of source and drain electrodes of a TFT, and the third wiring layer 388 may be formed of a layer of a pixel electrode in the pixel portion. However, there is no limitation on the formation of the layers, and for example, the third wiring layer 388 may be formed as a layer different from the layer of the pixel electrode.

Note that a connection relation between circuit elements in FIG. 7 is as illustrated in FIG. 6. Note that FIG. 7 illustrates the flip-flop circuit to which the first clock signal is input; therefore, connection to the control signal lines 354 to 356 is not illustrated.

In the layout view of the flip-flop circuit of FIG. 7, by controlling threshold voltage of the TFT 366 or the TFT 367 included in the logic circuit portion 361, an EDMOS circuit 373 can be formed. Typically, the EDMOS circuit 373 in which the

TFT 366 is a depletion type and the TFT 367 is an enhancement type is formed, and the TFTs 369 to 372 included in the switch portion 362 are dual-gate TFTs or depletion type TFTs. Note that in FIG. 6, the TFT 366 and the TFT 367 in the EDMOS circuit 373 are different from the TFTs in the EDMOS circuit illustrated in FIG. 2 in a connection position of the gate electrode of the depletion type TFT.

The TFT 366 or the TFT 367 is formed so as to be a dual-gate TFT and a potential of a back-gate electrode is controlled, so that a depletion type TFT or an enhancement type TFT can be formed.

In FIG. 7, a control signal line 390 which has the same potential as a back-gate electrode for controlling the threshold voltage of the TFT 366 is separately provided to form a depletion type. The TFT 366 is a dual-gate TFT, and a potential of the back-gate electrode is different from a potential of the power supply line 381 through which the power supply potential Vdd that is applied to the gate electrode is supplied.

FIG. 7 illustrates an example in which the TFTs 369 to 372 are dual-gate TFTs and the back-gate electrodes and the gate electrodes have the same potentials, and a potential of each of the back-gate electrodes is the same potential as that of the power supply line through which the power supply potential Vdd that is applied to the gate electrode is supplied.

In this manner, TFTs arranged in the pixel portion and the driver circuit of a display device can be formed using only n-channel TFTs in which an oxide semiconductor layer is used.

Further, the TFT 366 in the logic circuit portion 361 is a TFT for applying current in response to the power supply potential Vdd. The TFT 366 is formed to be a dual-gate TFT or a depletion type TFT to increase the flowing current, whereby miniaturization of the TFT can be achieved without reducing performance.

Further, in the TFTs included in the switch portion 362, the amount of current flowing in the TFTs can be increased and switching of on/off can be performed at high speed; therefore, an area occupied by the TFTs can be reduced without reducing performance. Accordingly, an area occupied by the circuit including the TFTs can also be reduced. Note that the TFTs 369 to 372 in the switch portion 362 may be formed to be dual-gate TFTs so that the semiconductor layer 385 is interposed between the first wiring layer 386 and the third wiring layer 388 as illustrated in the drawing.

An example that the dual-gate TFT has a structure in which the semiconductor layer 385 is interposed between the first wiring layer 386 and the third wiring layer 388 which have the same potential by being connected to each other through the contact hole 389 is illustrated in FIG. 7; however, the present invention is not limited to this structure. For example, a structure in which a control signal line is separately provided for the third wiring layer 388 to control a potential of the third wiring layer 388 independently from the first wiring layer 386 may be employed.

Note that in the layout view of the flip-flop circuit illustrated in FIG. 7, the shapes of the channel formation regions of the TFTs 363 to 372 may be U shapes (reversed C shapes or horseshoe shapes). In addition, although all the TFTs have the same size in FIG. 7, the size of each TFT which is connected to the output signal terminal S_(out), or the gate output terminal G_(out) may be changed as appropriate in accordance with the amount of a load of subsequent stage.

Next, operation of the shift register circuit illustrated in FIG. 5 is described with reference to a timing chart illustrated in FIG. 8. FIG. 8 illustrates the start pulse SSP and the first to fourth clock signals CLK1 to CLK4, which are supplied to the control signal lines 352 to 356 illustrated in FIG. 5, respectively, and the S_(out)s 1 to 5 output from the output signal terminals S_(out) of the flip-flop circuits of the first to fifth stages. Note that in description of FIG. 8, the reference numerals denoting the respective elements in FIG. 6 and FIG. 7 are used.

Note that FIG. 8 is a timing chart in the case where each TFT included in the flip-flop circuits is an n-channel TFT. Further, the first clock signal CLK1 is shifted from the fourth clock signal CLK4 by ¼ wavelength (a section divided by dotted lines) as illustrated.

First, in a period T1, the start pulse SSP is input to the flip-flop circuit of the first stage at an H level, and the logic circuit portion 361 turns the TFTs 369 and 371 on and the TFTs 370 and 372 off in the switch portion. At this time, since the first clock signal CLK1 is at an L level, the S_(out) 1 is at an L level.

Note that in the period T1, signals are not input to the IN terminals of the flip-flop circuits of the second and subsequent stages, so that the flip-flop circuits output L levels without operation. Note that description is made assuming that each flip-flop circuit of the shift register circuit outputs an L level in an initial state.

Next, in a period T2, the logic circuit portion 361 controls the switch portion 362 in the flip-flop circuit of the first stage in a manner similar to the period T1. In the period T2, the first clock signal CLK1 is at an H level, and thus the S_(out) 1 is at an H level. Further, in the period T2, the S_(out) 1 is input to the IN terminal of the flip-flop circuit of the second stage at an H level, and the logic circuit portion 361 turns the TFTs 369 and 371 on and the TFTs 370 and 372 off in the switch portion. At this time, since the second clock signal CLK2 is at an L level, the S_(out) 2 is at an L level.

Note that in the period T2, signals are not input to the IN terminals of the flip-flop circuits of the third and subsequent stages, so that the flip-flop circuits output L levels without operation.

Next, in a period T3, the logic circuit portion 361 controls the switch portion 362 so that a state of the period T2 is held in the flip-flop circuit of the first stage. Therefore, in the period T3, the first clock signal CLK1 is at an H level and the S_(out) 1 is at an H level. Further, in the period T3, the logic circuit portion 361 controls the switch portion 362 in the flip-flop circuit of the second stage in a manner similar to the period T2. In the period T3, since the second clock signal CLK2 is at an H level, the S_(out) 2 is at an H level. In addition, the S_(out) 2 is input to the IN terminal of the flip-flop circuit of the third stage at an H level in the period T3, and the logic circuit portion 361 turns the TFTs 369 and 371 on and the TFTs 370 and 372 off in the switch portion. At this time, the third clock signal CLK3 is at an L level, and thus the S_(out) 3 is at an L level.

Note that in the period T3, signals are not input to the IN terminals of the flip-flop circuits of the fourth and subsequent stages, so that the flip-flop circuits output L levels without operation.

Next, in the period T4, the logic circuit portion 361 controls the switch portion 362 so that a state of the period T3 is held in the flip-flop circuit of the first stage. Therefore, in the period T4, the first clock signal CLK1 is at an L level and the S_(out) 1 is at an L level. Further, in the period T4, the logic circuit portion 361 controls the switch portion 362 so that a state of the period T3 is held in the flip-flop circuit of the second stage. Therefore, in the period T4, the second clock signal CLK2 is at an H level and S_(out) 2 is at an H level. In addition, in the period T4, the logic circuit portion 361 controls the switch portion 362 in the flip-flop circuit of the third stage in a manner similar to the period T3. In the period T4, since the third clock signal CLK3 is at an H level, the S_(out) 3 is at an H level. The S_(out) 3 is input to the IN terminal of the flip-flop circuit of the fourth stage at an H level in the period T4, and the logic circuit portion 361 turns the TFTs 369 and 371 on and the TFTs 370 and 372 off in the switch portion 362. At this time, since the fourth clock signal CLK4 is at an L level, the S_(out) 4 is at an L level.

Note that in the period T4, signals are not input to the IN terminals of the flip-flop circuits of the fifth and subsequent stages, so that the flip-flop circuits output L levels without operation.

Next, in a period T5, the logic circuit portion 361 controls the switch portion 362 so that a state of the period T3 is held in the flip-flop circuit of the second stage. Therefore, in the period T5, the second clock signal CLK2 is at an L level and the S_(out) 2 is at an L level. Further, in the period T5, the logic circuit portion 361 controls the switch portion 362 so that a state of the period T4 is held in the flip-flop circuit of the third stage. Therefore, in the period T5, the third clock signal CLK3 is at an H level and the S_(out) 3 is at an H level. In addition, in the period T5, the logic circuit portion 361 controls the switch portion 362 in the flip-flop circuit of the fourth stage in a manner similar to the period T4. In the period T5, since the fourth clock signal CLK4 is at an H level, the S_(out) 4 is at an H level. The flip-flop circuits of the fifth and subsequent stages have a wiring connection and a timing of a signal to be input similar to those of the flip-flop circuits of the first to fourth stages; therefore, description thereof is omitted.

As illustrated in the shift register circuit of FIG. 5, the S_(out), 4 also functions as a reset signal of the flip-flop circuit of the first stage. In the period T5, the S_(out) 4 is at an H level and this signal is input to the reset terminal RES of the flip-flop circuit of the first stage. When the reset signal is input, the TFTs 369 and 371 are turned off and the TFTs 370 and 372 are turned on in the switch portion 362. Then, the S_(out) 1 of the flip-flop circuit of the first stage outputs an L level until input of the next start pulse SSP.

By the above-described operation, in the flip-flop circuits of the second and subsequent stages, the logic circuit portions are also reset based on the reset signals which are output from the flip-flop circuits of subsequent stages. As shown by the S_(out)s 1 to 5, a shift register circuit in which signals having waveforms shifted by ¼ wavelength of the clock signals are output can be formed.

When the flip-flop circuit has a structure in which an EDMOS circuit that is a combination of an enhancement type TFT and a depletion type TFT is provided in the logic circuit portion and a dual-gate TFT is provided in the switch portion, the amount of current flowing in the TFTs included in the logic circuit portion 361 can be increased and an area occupied by the TFTs and furthermore, an area occupied by the circuit including the TFTs can be reduced without reduction in performance. Further, in the TFT included in the switch portion 362, the amount of current flowing in the TFT can be increased and switching of on/off can be performed at high speed; therefore, an area occupied by the TFTs and furthermore, an area occupied by the circuit including the TFTs can be reduced without reduction in performance. Accordingly, a narrow frame, downsizing, high performance of a display device can be achieved.

Further, a latch circuit, a level shifter circuit, or the like can be provided in the signal line driver circuit illustrated in FIGS. 3A and 3B. A buffer portion is provided in the last stage through which a signal is transmitted from the signal line driver circuit to the pixel portion, and an amplified signal is transmitted from the signal line driver circuit to the pixel portion. Thus, when a TFT having large on current, typically a dual-gate TFT or a depletion type TFT is provided in the buffer portion, an area of the TFT can be reduced and an area occupied by the signal line driver circuit can be reduced. Accordingly, a narrow frame, downsizing, and high performance of a display device can be achieved. Note that since high-speed operation is required for the shift register which is part of the signal line driver circuit, the shift register is preferably mounted on a display device by use of an IC or the like.

In addition, this embodiment can be freely combined with Embodiment 1 or Embodiment 2.

Embodiment 4

In Embodiment 4, a method for manufacturing a display device including the second thin film transistor 170 described in Embodiment 1 will be described with reference to FIGS. 9A to 9C, FIGS. 10A to 10C, FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIGS. 15A1, 15A2, 15B1, and 15B2, and FIG. 16.

In FIG. 9A, a glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like can be used as a substrate 100 having a light-transmitting property.

Next, after a conductive layer is formed over an entire surface of the substrate 100, a resist mask is formed by a first photolithography step. Then, unnecessary portions are removed by etching, thereby forming wirings and electrodes (a gate wiring including the gate electrode 101, a capacitor wiring 108, and a first terminal 121). At this time, etching is performed so that at least an end portion of the gate electrode 101 is tapered. A cross-sectional view at this stage is illustrated in FIG. 9A. Note that FIG. 11 is a top view at this stage.

The gate wiring including the gate electrode 101, the capacitor wiring 108, and the first terminal 121 in the terminal portion are desirably formed of a low-resistant conductive material such as aluminum (Al) or copper (Cu). However, aluminum itself has the disadvantages of low heat resistance, being easily corroded, and the like; thus, it is used in combination with a conductive material having heat resistance. As the conductive material having heat resistance, it is possible to use an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing any of these elements as its component, an alloy film containing a combination of any of these elements, or a nitride containing any of these elements as its component.

Then, the gate insulating layer 102 is entirely formed over the gate electrode 101. The gate insulating layer 102 is formed to a thickness of 50 nm to 400 nm by a sputtering method or the like. When yield of the thin film transistor is prioritized, the thickness of the gate insulating layer 102 is preferably large.

For example, as the gate insulating layer 102, a silicon oxide film is formed to a thickness of 100 nm by a sputtering method. It is needless to say that the gate insulating layer 102 is not limited to such a silicon oxide film, and another insulating film such as a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or a tantalum oxide film may be used to form a single-layer structure or a stacked structure. When a silicon oxynitride film, a silicon nitride film, or the like is used as the gate insulating layer 102, an impurity from the glass substrate, sodium for example, can be blocked from diffusing into and entering an oxide semiconductor to be formed later.

Next, a resist mask is formed by a second photolithography step. Then, unnecessary portions are removed by etching, thereby forming a contact hole which reaches the wiring or the electrode formed of the same material as the gate electrode. This contact hole is provided for directly connecting to a conductive film to be formed later. For example, in a driver circuit portion, the contact hole is formed in the case of forming a thin film transistor in which a gate electrode is directly in contact with a source electrode or a drain electrode, or in the case of forming a terminal which is electrically connected to a gate wiring in the terminal portion. Note that an example in which the second photolithography step is performed to form the contact hole for directly connecting to the conductive film to be formed later is described here.

However, a contact hole reaching a gate electrode layer may be formed later in the same step as the step in which a contact hole for connection to a pixel electrode is formed, and electrical connection may be performed using the same material as the pixel electrode without particular limitations. When the electrical connection is performed using the same material as the pixel electrode, the number of masks can be reduced by one.

Next, a conductive film of a metal material is formed over the gate insulating layer 102 by a sputtering method or a vacuum evaporation method. Here, the conductive film has a three-layer structure of a Ti film, an aluminum film containing Nd, and a Ti film. As a material for the conductive film, an element selected from Al, Cr, Ta, Ti, Mo, and W; an alloy containing any of the above elements as its component; an alloy film containing a combination of any of the above elements; and the like can be given. Further, the conductive film may have a two-layer structure, and a titanium film may be stacked over an aluminum film. Alternatively, the conductive film may have a single-layer structure of an aluminum film containing silicon or a single-layer structure of a titanium film.

Next, a resist mask is formed by a third photolithography step. Then, unnecessary portions are removed by etching, thereby forming a source electrode layer 105 a, a drain electrode layer 105 b, and a connection electrode 120. Wet etching or dry etching is employed as an etching method at this time. Here, an ammonium hydrogen peroxide mixture (hydrogen peroxide:ammonium:water=5:2:2) is used as an etchant for the Ti films, and a solution in which phosphoric acid, acetic acid, and nitric acid are mixed is used for etching of the aluminum film containing Nd. By this wet etching, the conductive film in which the Ti film, the Al—Nd film, and the Ti film are sequentially stacked is etched, thereby forming the source electrode layer 105 a and the drain electrode layer 105 b. A cross-sectional view at this stage is illustrated in FIG. 9B. Note that FIG. 12 is a top view at this stage.

In the terminal portion, the connection electrode 120 is directly connected to the first terminal 121 in the terminal portion through the contact hole formed in the gate insulating layer. Note that although not illustrated here, a source wiring or a drain wiring, and a gate electrode of the thin film transistor in the driver circuit are directly connected through the same steps as the above-described steps.

Next, after removal of the resist mask, plasma treatment is preferably performed to remove dust and the like attached to surfaces of the source electrode layer 105 a and the drain electrode layer 105 b. A cross-sectional view at this stage is illustrated in FIG. 9C. Here, reverse sputtering in which an argon gas is introduced and plasma is generated with an RF power is performed, so that the exposed gate insulating layer is subjected to plasma treatment.

Next, after the plasma treatment, an oxide semiconductor film is formed. The oxide semiconductor film is formed without being exposed to the atmosphere after the plasma treatment, which is advantageous in that dust and the like are not attached to the interface between the gate insulating layer and the oxide semiconductor film. Here, with the use of an oxide semiconductor target containing In (indium), Ga (gallium), and Zn (zinc) (In₂O₃:Ga₂O₃:ZnO=1:1:1), which has a diameter of 8 inches, deposition is performed in an argon atmosphere or an oxygen atmosphere at a distance between the substrate and the target of 170 mm, a pressure of 0.4 Pa, and a direct current (DC) power supply of 0.5 kW. Note that a pulsed direct current (DC) power supply is preferably used to reduce dust and obtain a uniform distribution of film thickness. The thickness of the oxide semiconductor film is 5 nm to 200 nm, and in this embodiment, the thickness of the oxide semiconductor film is 100 nm.

Next, a resist mask is formed by a fourth photolithography step. Then, unnecessary portions are removed by etching, thereby forming the oxide semiconductor layer 103. Here, unnecessary portions are removed by wet etching using ITO07N (manufactured by KANTO CHEMICAL CO., INC.), thereby forming the oxide semiconductor layer 103. Note that etching here is not limited to wet etching and dry etching may also be performed. After that, the resist mask is removed.

In the fourth photolithography step, a second terminal 122 that is made of the same material as the source and drain electrode layers 105 a and 105 b remains in the terminal portion. Note that the second terminal 122 is electrically connected to a source wiring (a source wiring including the source and drain electrode layers 105 a and 105 b).

Next, heat treatment is preferably performed at 200° C. to 600° C., typically 300° C. to 500° C. For example, heat treatment is performed in a furnace for 1 hour at 350° C. in a nitrogen atmosphere or an air atmosphere. Through the above-described steps, the thin film transistor 170 in which the oxide semiconductor layer 103 is used as a channel formation region can be manufactured. A cross-sectional view at this stage is illustrated in FIG. 10A. Note that a top view at this stage is illustrated in FIG. 13. Note that there is no particular limitation on timing of the heat treatment as long as it is performed after the formation of the oxide semiconductor film, and for example, the heat treatment may be performed after formation of a protective insulating film.

Furthermore, oxygen radical treatment may be performed on an exposed surface of the oxide semiconductor layer 103. By the oxygen radical treatment, the thin film transistor can be normally off. Further, by radical treatment, damage to the oxide semiconductor layer 103 due to the etching can be repaired. The radical treatment is preferably performed in an O₂ and/or N₂O atmosphere, more preferably, in an atmosphere of N₂, He, and/or Ar each containing oxygen. Alternatively, the radical treatment may be performed in an atmosphere in which Cl₂ and/or CF₄ are/is added to any of the above atmospheres. Note that the radical treatment may be performed with no bias applied.

Next, a protective insulating layer 107 which covers the second thin film transistor 170 is formed. The protective insulating layer 107 may be formed of a single layer of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, a tantalum oxide film, or the like, which is obtained by a sputtering method or the like, or stacked layers of these films. In the thin film transistors in part of the driver circuit, the protective insulating layer 107 functions as a second gate insulating layer and a second gate electrode is formed thereover. The protective insulating layer 107 has a thickness of 50 nm to 400 nm When yield of the thin film transistor is prioritized, the thickness of the protective insulating layer 107 is preferably large. Further, when a silicon oxynitride film, a silicon nitride film, or the like is used as the protective insulating layer 107, an impurity attached for some reason after the formation of the protective insulating layer 107, e.g., sodium, can be blocked from diffusing into and entering the oxide semiconductor.

Then, a fifth photolithography step is performed to form a resist mask, and the protective insulating layer 107 is etched to form a contact hole 125 reaching the drain electrode layer 105 b. In addition, a contact hole 126 reaching the connection electrode 120 and a contact hole 127 reaching the second terminal 122 are also formed by the etching here. A cross-sectional view at this stage is illustrated in FIG. 10B.

Next, the resist mask is removed, and then a transparent conductive film is formed. The transparent conductive film is formed of indium oxide (In₂O₃), indium oxide-tin oxide alloy (In₂O₃—SnO₂, abbreviated to ITO), or the like by a sputtering method, a vacuum evaporation method, or the like. Such a material is etched with a hydrochloric acid-based solution. However, since a residue is easily generated particularly in etching ITO, indium oxide-zinc oxide alloy (In₂O₃—ZnO) may be used to improve etching processability.

Next, a resist mask is formed by a sixth photolithography step. Then, unnecessary portions are removed by etching, thereby forming the pixel electrode 110 in the pixel portion. In the sixth photolithography step, in the driver circuit, the same material as that of the pixel electrode 110 is used for part of the circuit to form an electrode layer (a back-gate electrode) for controlling the threshold value over the oxide semiconductor layer. Note that the thin film transistor having the back-gate electrode is described in Embodiment 1 with reference to FIG. 1A; therefore, detailed description thereof is omitted here.

In the sixth photolithography step, a storage capacitor is formed of the capacitor wiring 108 and the pixel electrode 110 by using the gate insulating layer 102 and the protective insulating layer 107 in the capacitor portion as dielectrics. Note that an example in which the storage capacitor is formed of the capacitor wiring 108 and the pixel electrode 110 by using the gate insulating layer 102 and the protective insulating layer 107 as the dielectrics is described here. However, there is no particular limitation and a structure may also be employed, in which an electrode including the same material as the source electrode or the drain electrode is provided above the capacitor wiring and a storage capacitor is formed of the electrode and the capacitor wiring by using the gate insulating layer 102 therebetween as a dielectric, thereby electrically connecting the electrode and the pixel electrode.

Furthermore, in the sixth photolithography step, the first terminal and the second terminal are covered with the resist mask so that transparent conductive films 128 and 129 remain in the terminal portion. The transparent conductive films 128 and 129 function as electrodes or wirings connected to an FPC. The transparent conductive film 128 formed over the connection electrode 120 which is directly connected to the first terminal 121 is a connection terminal electrode which functions as an input terminal of the gate wiring. The transparent conductive film 129 formed over the second terminal 122 is a connection terminal electrode which functions as an input terminal of the source wiring.

Then, the resist mask is removed. A cross-sectional view at this stage is illustrated in FIG. 10C. Note that FIG. 14 is a top view at this stage.

FIGS. 15A1 and 15A2 respectively illustrate a cross-sectional view and a top view of a gate wiring terminal portion at this stage. FIG. 15A1 is a cross-sectional view taken along line C1-C2 of FIG. 15A2. In FIG. 15A1, a transparent conductive film 155 formed over a protective insulating film 154 is a connection terminal electrode functioning as an input terminal. Further, in the terminal portion of FIG. 15A1, a first terminal 151 made of the same material as the gate wiring and a connection electrode 153 made of the same material as the source wiring overlap with each other with a gate insulating layer 152 interposed therebetween, and are in direct contact with each other so as to be electrically connected. In addition, the connection electrode 153 and the transparent conductive film 155 are in direct contact with each other through a contact hole provided in the protective insulating film 154 so as to be electrically connected.

FIGS. 15B1 and 15B2 respectively illustrate a cross-sectional view and a top view of a source wiring terminal portion. FIG. 15B1 is a cross-sectional view taken along line D1-D2 of FIG. 15B2. In FIG. 15B1, the transparent conductive film 155 formed over the protective insulating film 154 is a connection terminal electrode functioning as an input terminal Further, in the terminal portion of FIG. 15B1, an electrode 156 made of the same material as the gate wiring is formed below a second terminal 150 which is electrically connected to the source wiring and overlaps with the second terminal 150 with the gate insulating layer 152 interposed therebetween. The electrode 156 is not electrically connected to the second terminal 150, and a capacitor to prevent noise or static electricity can be formed if the potential of the electrode 156 is set to a potential different from that of the second terminal 150, such as floating, GND, or 0 V. The second terminal 150 is electrically connected to the transparent conductive film 155 with the protective insulating film 154 interposed therebetween.

A plurality of gate wirings, source wirings, and capacitor wirings are provided depending on the pixel density. Also in the terminal portion, the first terminal at the same potential as the gate wiring, the second terminal at the same potential as the source wiring, the third terminal at the same potential as the capacitor wiring, and the like are each arranged in plurality. There is no particular limitation on the number of each of the terminals, and the number of the terminals may be determined by a practitioner as appropriate.

Through these six photolithography steps, the second thin film transistor 170 which is a bottom-gate n-channel thin film transistor and the storage capacitor can be completed using the six photomasks. By disposing the thin film transistor and the storage capacitor in each pixel of a pixel portion in which pixels are arranged in a matrix form, one of substrates for manufacturing an active matrix display device can be obtained. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the case of electrically connecting to the gate wiring by using the same material as the pixel electrode, the third photolithography step can be omitted. Therefore, through the five photolithography steps, the second thin film transistor which is a bottom-gate n-channel thin film transistor and the storage capacitor can be completed using the five photomasks.

Further, in the case where a material of the second gate electrode is different from a material of the pixel electrode as illustrated in FIG. 1C, one photolithography step is added, so that one photomask is added.

In the case of manufacturing an active matrix liquid crystal display device, an active matrix substrate and a counter substrate provided with a counter electrode are bonded to each other with a liquid crystal layer interposed therebetween. Note that a common electrode electrically connected to the counter electrode on the counter substrate is provided over the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal portion. The fourth terminal is provided so that the common electrode is fixed to a predetermined potential such as GND or 0 V.

Further, the pixel structure is not limited to that of FIG. 14, and an example of a top view which is different from FIG. 14 is illustrated in FIG. 16. FIG. 16 illustrates an example in which a capacitor wiring is not provided and a pixel electrode overlaps with a gate wiring of an adjacent pixel with a protective insulating film and a gate insulating layer interposed therebetween to form a storage capacitor. In that case, the capacitor wiring and the third terminal connected to the capacitor wiring can be omitted. Note that in FIG. 16, the same parts as those in FIG. 14 are denoted by the same reference numerals.

In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form are driven to form a display pattern on a screen. Specifically, voltage is applied between a selected pixel electrode and a counter electrode corresponding to the pixel electrode, so that a liquid crystal layer provided between the pixel electrode and the counter electrode is optically modulated and this optical modulation is recognized as a display pattern by an observer.

In displaying moving images, a liquid crystal display device has a problem that a long response time of liquid crystal molecules themselves causes afterimages or blurring of moving images. In order to improve the moving-image characteristics of a liquid crystal display device, a driving method called black insertion is employed in which black is displayed on the whole screen every other frame period.

Alternatively, a driving method called double-frame rate driving may be employed in which the vertical cycle is 1.5 or 2 times as long as usual to improve the moving-image characteristics.

Further alternatively, in order to improve the moving-image characteristics of a liquid crystal display device, a driving method may be employed, in which a plurality of LEDs (light-emitting diodes) or a plurality of EL light sources are used to form a surface light source as a backlight, and each light source of the surface light source is independently driven in a pulsed manner in one frame period. As the surface light source, three or more kinds of LEDs may be used and an LED emitting white light may be used. Since a plurality of LEDs can be controlled independently, the light emission timing of LEDs can be synchronized with the timing at which a liquid crystal layer is optically modulated. According to this driving method, LEDs can be partly turned off; therefore, an effect of reducing power consumption can be obtained particularly in the case of displaying an image having a large part on which black is displayed.

By combining these driving methods, the display characteristics of a liquid crystal display device, such as moving-image characteristics, can be improved as compared to those of conventional liquid crystal display devices.

The n-channel transistor obtained in this embodiment uses an In—Ga—Zn—O-based non-single-crystal film for a channel formation region and has favorable dynamic characteristics. Accordingly, these driving methods can be applied in combination with the n-channel transistor of this embodiment.

In manufacturing a light-emitting display device, one electrode (also referred to as a cathode) of an organic light-emitting element is set to a low power supply potential such as GND or 0 V; thus, a terminal portion is provided with a fourth terminal for setting the cathode to a low power supply potential such as GND or 0 V. Also in the case of manufacturing a light-emitting display device, a power supply line is provided in addition to a source wiring and a gate wiring. Accordingly, the terminal portion is provided with a fifth terminal electrically connected to the power supply line.

With use of the thin film transistor using the oxide semiconductor in a gate line driver circuit or a source line driver circuit, manufacturing cost is reduced. Then, by directly connecting a gate electrode of the thin film transistor used in the driver circuit with a source wiring or a drain wiring, the number of contact holes can be reduced, so that a display device in which an area occupied by the driver circuit is reduced can be provided.

Accordingly, by applying this embodiment, a display device with excellent electric characteristics can be provided at lower cost.

This embodiment can be freely combined with any of Embodiment 1, Embodiment 2, and Embodiment 3.

Embodiment 5

In this embodiment, an example of electronic paper will be described as a semiconductor device.

FIG. 17 illustrates active matrix electronic paper as an example of a semiconductor device which is different from a liquid crystal display device. A thin film transistor 581 used for a pixel portion of a semiconductor device can be manufactured in a manner similar to the thin film transistor in the pixel portion described in Embodiment 4 and is a thin film transistor including an In—Ga—Zn—O-based non-single-crystal film as a semiconductor layer. Further, as described in Embodiment 1, a pixel portion and a driver circuit can be manufactured over the same substrate, and thus electronic paper can be realized at lower manufacturing cost.

The electronic paper in FIG. 17 is an example of a display device using a twisting ball display system. The twisting ball display system refers to a method in which spherical particles each colored in black and white are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control the orientation of the spherical particles, so that display is performed.

The thin film transistor 581 is a bottom-gate thin film transistor, and a source electrode layer or a drain electrode layer is in contact with a first electrode layer 587 through an opening formed in insulating layers 583, 584, and 585, whereby the thin film transistor 581 is electrically connected to the first electrode layer 587. Between a pair of electrodes 580 and 596, spherical particles 589 each having a black region 590 a, a white region 590 b, and a cavity 594 around the regions which is filled with liquid are provided between the first electrode layer 587 and a second electrode layer 588. A space around the spherical particles 589 is filled with a filler 595 such as a resin (see FIG. 17).

Instead of the twisting ball, an electrophoretic element can also be used. A microcapsule having a diameter of approximately 10 μm to 200 μm in which transparent liquid, positively-charged white microparticles, and negatively-charged black microparticles are encapsulated, is used. In the microcapsule which is provided between the first electrode layer and the second electrode layer, when an electric field is applied between the first electrode layer and the second electrode layer, the white microparticles and the black microparticles move to opposite sides, so that white or black can be displayed. A display element using this principle is an electrophoretic display element and is called electronic paper. The electrophoretic display element has higher reflectance than a liquid crystal display element, and thus, an auxiliary light is unnecessary, power consumption is low, and a display portion can be recognized even in a dim place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which may be referred to simply as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source.

Through the above-described steps, electronic paper can be manufactured as a semiconductor device at lower manufacturing cost.

This embodiment can be implemented in combination with the structure described in Embodiment 1 or Embodiment 2 as appropriate.

Embodiment 6

In this embodiment, an example of a light-emitting display device will be described as a semiconductor device. As a display element included in a display device, a light-emitting element utilizing electroluminescence is described here.

Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. Then, the carriers (electrons and holes) are recombined, so that the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. A dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that an example of using an organic EL element as a light-emitting element is described here.

FIG. 18 illustrates an example of a pixel structure as an example of a semiconductor device, which can be driven by a digital time grayscale method.

The structure and operation of a pixel which can be driven by a digital time grayscale method is be described. An example is shown here in which one pixel includes two n-channel transistors using an oxide semiconductor layer (an In—Ga—Zn—O-based non-single-crystal film) for a channel formation region.

A pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitor 6403. A gate of the switching transistor 6401 is connected to a scan line 6406, a first electrode (one of a source electrode and a drain electrode) of the switching transistor 6401 is connected to a signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) of the switching transistor 6401 is connected to a gate of the driving transistor 6402. The gate of the driving transistor 6402 is connected to a power supply line 6407 through the capacitor 6403, a first electrode of the driving transistor 6402 is connected to the power supply line 6407, and a second electrode of the driving transistor 6402 is connected to a first electrode (pixel electrode) of the light-emitting element 6404. A second electrode of the light-emitting element 6404 corresponds to a common electrode 6408.

Note that the second electrode (the common electrode 6408) of the light-emitting element 6404 is set to a low power supply potential. Note that the low power supply potential is a potential satisfying the low power supply potential<a high power supply potential when the high power supply potential set to the power supply line 6407 is a reference. For example, GND or 0 V may be set as the low power supply potential. The difference between the high power supply potential and the low power supply potential is applied to the light-emitting element 6404 to flow current in the light-emitting element 6404, whereby the light-emitting element 6404 emits light. Thus, each potential is set so that the difference between the high power supply potential and the low power supply potential is equal to or higher than a forward threshold voltage.

Note that when the gate capacitor of the driving transistor 6402 is used as a substitute for the capacitor 6403, the capacitor 6403 can be omitted. The gate capacitor of the driving transistor 6402 may be formed between a channel region and a gate electrode.

In the case of using a voltage-input voltage driving method, a video signal is input to the gate of the driving transistor 6402 to turn the driving transistor 6402 completely on or off. That is, the driving transistor 6402 operates in a linear region, and thus, voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that voltage higher than or equal to (power supply line voltage+V_(th) of the driving transistor 6402) is applied to the signal line 6405.

In the case of using an analog grayscale method instead of the digital time grayscale method, the same pixel structure as in FIG. 18 can be employed by inputting signals in a different manner.

In the case of using the analog grayscale method, voltage higher than or equal to (forward voltage of the light-emitting element 6404+V_(th) of the driving transistor 6402) is applied to the gate of the driving transistor 6402. The forward voltage of the light-emitting element 6404 refers to voltage to obtain a desired luminance, and includes at least a forward threshold voltage. By inputting a video signal to allow the driving transistor 6402 to operate in a saturation region, current can flow in the light-emitting element 6404. In order to allow the driving transistor 6402 to operate in the saturation region, the potential of the power supply line 6407 is higher than a gate potential of the driving transistor 6402. Since the video signal is an analog signal, current flows in the light-emitting element 6404 in response to the video signal, and the analog grayscale method can be performed.

Note that the pixel structure is not limited to that illustrated in FIG. 18. For example, the pixel in FIG. 18 can further include a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like.

Next, structures of the light-emitting elements are described with reference to FIGS. 19A, 19B, and 19C. Here, cross-sectional structures of pixels are described taking a case where a driving TFT is the thin film transistor 170 illustrated in FIG. 1B, as an example. TFTs 7001, 7011, and 7021, which are driving TFTs used for semiconductor devices in FIGS. 19A, 19B, and 19C, respectively, can be manufactured in a manner similar to the thin film transistor 170 described in Embodiment 1, and are thin film transistors with excellent electric characteristics, each including an In—Ga—Zn—O-based non-single-crystal film as a semiconductor layer.

In order to extract light emitted from the light-emitting element, at least one of the anode and the cathode is required to be transparent. A thin film transistor and a light-emitting element are formed over a substrate. A light-emitting element can have a top emission structure in which light is extracted through the surface opposite to the substrate; a bottom emission structure in which light is extracted through the surface on the substrate side; or a dual emission structure in which light is extracted through the surface opposite to the substrate and the surface on the substrate side. The pixel structure illustrated in FIG. 18 can be applied to a light-emitting element having any of these emission structures.

A light-emitting element having a top emission structure is described with reference to FIG. 19A.

FIG. 19A is a cross-sectional view of a pixel in the case where the driving TFT 7001 is the thin film transistor 170 illustrated in FIG. 1B and light from a light-emitting element 7002 is emitted through an anode 7005. In FIG. 19A, a cathode 7003 of the light-emitting element 7002 is electrically connected to the driving TFT 7001, and a light-emitting layer 7004 and the anode 7005 are stacked in this order over the cathode 7003. The cathode 7003 can be made of a variety of conductive materials as long as they have a low work function and reflect light. For example, Ca, Al, MgAg, AlLi, or the like is desirably used. The light-emitting layer 7004 may be formed using a single layer or a plurality of layers stacked. When the light-emitting layer 7004 is formed using a plurality of layers, the light-emitting layer 7004 is formed by stacking an electron-injecting layer, an electron-transporting layer, a light-emitting layer, a hole-transporting layer, and a hole-injecting layer in this order over the cathode 7003.

Not all of these layers need to be provided. The anode 7005 is made of a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter, referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.

The light-emitting element 7002 corresponds to a region where the cathode 7003 and the anode 7005 sandwich the light-emitting layer 7004. In the case of the pixel illustrated in FIG. 19A, light from the light-emitting element 7002 is emitted through the anode 7005 as indicated by an arrow.

Note that a second gate electrode provided over the oxide semiconductor layer in the driver circuit is preferably formed of the same material as the cathode 7003, whereby steps can be simplified.

Next, a light-emitting element having a bottom emission structure is described with reference to FIG. 19B. FIG. 19B is a cross-sectional view of a pixel in the case where the driving TFT 7011 is the thin film transistor illustrated in FIG. 1A and light from a light-emitting element 7012 is emitted through a cathode 7013. In FIG. 19B, the cathode 7013 of the light-emitting element 7012 is formed over a light-transmitting conductive film 7017 which is electrically connected to the driving TFT 7011, and a light-emitting layer 7014 and an anode 7015 are stacked in this order over the cathode 7013. A light-blocking film 7016 for reflecting or blocking light may be formed to cover the anode 7015 when the anode 7015 has a light-transmitting property. For the cathode 7013, various materials can be used, like in the case of FIG. 19A, as long as they are conductive materials having a low work function. Note that the cathode 7013 is formed to have a thickness that can transmit light (preferably, approximately 5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nm can be used as the cathode 7013. Similarly to the case of FIG. 19A, the light-emitting layer 7014 may be formed using either a single layer or a plurality of layers stacked. The anode 7015 is not required to transmit light, but can be made of a light-transmitting conductive material like in the case of FIG. 19A. As the light-blocking film 7016, a metal which reflects light or the like can be used for example; however, it is not limited to a metal film. For example, a resin to which black pigments are added can also be used.

The light-emitting element 7012 corresponds to a region where the cathode 7013 and the anode 7015 sandwich the light-emitting layer 7014. In the case of the pixel illustrated in FIG. 19B, light from the light-emitting element 7012 is emitted through the cathode 7013 side as indicated by an arrow.

Note that the second gate electrode provided over the oxide semiconductor layer in the driver circuit is preferably formed of the same material as the cathode 7013, whereby steps can be simplified.

Next, a light-emitting element having a dual emission structure will be described with reference to FIG. 19C. In FIG. 19C, a cathode 7023 of a light-emitting element 7022 is formed over a light-transmitting conductive film 7027 which is electrically connected to the driving TFT 7021, and a light-emitting layer 7024 and an anode 7025 are stacked in this order over the cathode 7023. Like in the case of FIG. 19A, the cathode 7023 can be made of a variety of conductive materials as long as they have a low work function. Note that the cathode 7023 is formed to have a thickness that can transmit light. For example, a film of Al having a thickness of 20 nm can be used as the cathode 7023. Like in FIG. 19A, the light-emitting layer 7024 may be formed using either a single layer or a plurality of layers stacked. The anode 7025 can be made of a light-transmitting conductive material like in the case of FIG. 19A.

The light-emitting element 7022 corresponds to a region where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap with one another. In the case of the pixel illustrated in FIG. 19C, light from the light-emitting element 7022 is emitted through both the anode 7025 and the cathode 7023 as indicated by arrows.

Note that the second gate electrode provided over the oxide semiconductor layer in the driver circuit is preferably formed of the same material as the conductive film 7027, whereby steps can be simplified. Alternatively, the second gate electrode provided over the oxide semiconductor layer in the driver circuit is preferably formed of stacked layers using the same materials as the conductive film 7027 and a cathode 7023, whereby steps can be simplified and wiring resistance can also be reduced.

Note that although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.

Note that in this embodiment, an example in which a thin film transistor (a driving TFT) which controls the driving of a light-emitting element is electrically connected to the light-emitting element is described, but a structure in which a current controlling TFT is connected between the driving TFT and the light-emitting element may be employed.

Note that the structure of the semiconductor device described in this embodiment is not limited to those illustrated in FIGS. 19A, 19B, and 19C, and can be modified in various ways based on the spirit of the disclosed techniques.

Next, a top view and a cross-sectional view of a light-emitting display panel (also referred to as a light-emitting panel) which corresponds to one embodiment of the semiconductor device will be described with reference to FIGS. 20A and 20B. FIG. 20A is a top view of a panel in which a thin film transistor and a light-emitting element are sealed between a first substrate and a second substrate with a sealant. FIG. 20B is a cross-sectional view taken along line H-I of FIG. 20A.

A sealant 4505 is provided so as to surround a pixel portion 4502, signal line driver circuits 4503 a and 4503 b, and scan line driver circuits 4504 a and 4504 b, which are provided over a first substrate 4501. In addition, a second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b. Accordingly, the pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b are sealed together with a filler 4507, by the first substrate 4501, the sealant 4505, and the second substrate 4506. It is preferable that a display device be thus packaged (sealed) with a protective film (such as a bonding film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the display device is not exposed to the outside air.

The pixel portion 4502, the signal line driver circuits 4503 a and 4503 b, and the scan line driver circuits 4504 a and 4504 b formed over the first substrate 4501 each include a plurality of thin film transistors, and a thin film transistor 4510 included in the pixel portion 4502 and a thin film transistor 4509 included in the signal line driver circuit 4503 a are illustrated as an example in FIG. 20B.

As the thin film transistors 4509 and 4510, highly reliable thin film transistors described in Embodiment 1 including In—Ga—Zn—O-based non-single-crystal films as semiconductor layers can be used. Further, the thin film transistor 4509 includes gate electrodes above and below the semiconductor layer as described in Embodiment 1 with reference to FIG. 1B.

Moreover, reference numeral 4511 denotes a light-emitting element. A first electrode layer 4517 that is a pixel electrode included in the light-emitting element 4511 is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4510. Note that a structure of the light-emitting element 4511 is not limited to the stacked structure shown in this embodiment, which includes the first electrode layer 4517, an electroluminescent layer 4512, and the second electrode layer 4513. The structure of the light-emitting element 4511 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4511, or the like.

A partition wall 4520 is made of an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition wall 4520 be formed of a photosensitive material to have an opening over the first electrode layer 4517 so that a sidewall of the opening is formed as an inclined surface with continuous curvature.

The electroluminescent layer 4512 may be formed using a single layer or a plurality of layers stacked.

A protective film may be formed over the second electrode layer 4513 and the partition wall 4520 in order to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from entering into the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, a variety of signals and potentials are supplied to the signal line driver circuits 4503 a and 4503 b, the scan line driver circuits 4504 a and 4504 b, or the pixel portion 4502 from FPCs 4518 a and 4518 b.

In this embodiment, a connection terminal electrode 4515 is formed using the same conductive film as the first electrode layer 4517 of the light-emitting element 4511, and a terminal electrode 4516 is formed using the same conductive film as the source and drain electrode layers included in the thin film transistors 4509 and 4510.

The connection terminal electrode 4515 is electrically connected to a terminal of the FPC 4518 a through an anisotropic conductive film 4519.

The second substrate 4506 located in the direction in which light is extracted from the light-emitting element 4511 needs to have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

As the filler 4507, an ultraviolet curable resin or a thermosetting resin can be used, in addition to an inert gas such as nitrogen or argon. For example, PVC (polyvinyl chloride), acrylic, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used.

If needed, an optical film, such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter, may be provided as appropriate on a light-emitting surface of the light-emitting element. Furthermore, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.

The signal line driver circuits 4503 a and 4503 b and the scan line driver circuits 4504 a and 4504 b may be mounted as driver circuits formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a single crystal semiconductor substrate or an insulating substrate which is separately prepared.

Alternatively, only the signal line driver circuits or part thereof, or only the scan line driver circuits or part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated in FIGS. 20A and 20B.

Through the above-described steps, a light-emitting display device (a display panel) can be manufactured at lower manufacturing cost.

This embodiment can be implemented in combination with the structure described in Embodiment 1 or Embodiment 2 as appropriate.

Embodiment 7

In this embodiment, a top view and a cross-sectional view of a liquid crystal display panel which corresponds one embodiment of the semiconductor device will be described with reference to FIGS. 21A1, 21A2 and 21B. FIGS. 21A1 and 21A2 are top views of a panel in which thin film transistors 4010 and 4011 each including the In—Ga—Zn—O-based non-single-crystal film formed over a first substrate 4001, which is described in Embodiment 1, as a semiconductor layer, and a liquid crystal element 4013 are sealed between the first substrate 4001 and a second substrate 4006 with a sealant 4005. FIG. 21B is a cross-sectional view taken along line M-N of FIGS. 21A1 and 21A2.

The sealant 4005 is provided to surround a pixel portion 4002 and a scan line driver circuit 4004 that are provided over the first substrate 4001. The second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with a liquid crystal layer 4008, by the first substrate 4001, the sealant 4005, and the second substrate 4006. A signal line driver circuit 4003 that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared is mounted in a region different from the region surrounded by the sealant 4005 over the first substrate 4001.

Note that there is no particular limitation on the connection method of a driver circuit which is separately formed, and COG, wire bonding, TAB, or the like can be used. FIG. 21A1 illustrates an example of mounting the signal line driver circuit 4003 by COG, and FIG. 21A2 illustrates an example of mounting the signal line driver circuit 4003 by TAB.

The pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 each include a plurality of thin film transistors. FIG. 21B illustrates the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scan line driver circuit 4004. Insulating layers 4020 and 4021 are provided over the thin film transistors 4010 and 4011.

As the thin film transistors 4010 and 4011, the thin film transistor described in Embodiment 1 including an In—Ga—Zn—O-based non-single-crystal film as semiconductor layer can be used. The thin film transistor 4011 corresponds to the thin film transistor including the back-gate electrode illustrated in FIG. 2A of Embodiment 2.

A pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. A counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. A portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap with one another corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are provided with an insulating layer 4032 and an insulating layer 4033, respectively, each of which functions as an alignment film. The liquid crystal layer 4008 is sandwiched between the pixel electrode layer 4030 and the counter electrode layer 4031 with the insulating layers 4032 and 4033 interposed therebetween.

Note that the first substrate 4001 and the second substrate 4006 can be made of glass, metal (typically, stainless steel), ceramic, or plastic. As plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. Alternatively, a sheet with a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

Reference numeral 4035 denotes a columnar spacer obtained by selectively etching an insulating film and is provided to control the distance between the pixel electrode layer 4030 and the counter electrode layer 4031 (a cell gap). Alternatively, a spherical spacer may be used. The counter electrode layer 4031 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 4010. With the use of the common connection portion, the counter electrode layer 4031 is electrically connected to the common potential line through conductive particles provided between the pair of substrates. Note that the conductive particles are contained in the sealant 4005.

Alternatively, a liquid crystal showing a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of the liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase is only generated within a narrow range of temperature, a liquid crystal composition containing a chiral agent at 5 wt % or more is used for the liquid crystal layer 4008 in order to improve the temperature range. The liquid crystal composition which includes a liquid crystal showing a blue phase and a chiral agent has a small response time of 10 μs to 100 μs, has optical isotropy, which makes the alignment process unneeded, and has a small viewing angle dependence.

Note that although an example of a transmissive liquid crystal display device is described in this embodiment, this embodiment can also be applied to a reflective liquid crystal display device or a semi-transmissive liquid crystal display device.

In this embodiment, an example of the liquid crystal display device is shown in which a polarizing plate is provided on the outer surface of the substrate (on the viewer side) and a coloring layer and an electrode layer used for a display element are provided on the inner surface of the substrate in this order; however, the polarizing plate may be provided on the inner surface of the substrate. The stacked structure of the polarizing plate and the coloring layer is not limited to that shown in this embodiment and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of manufacturing steps. Furthermore, a light-blocking film functioning as a black matrix may be provided.

In this embodiment, in order to reduce the surface roughness of the thin film transistor and to improve the reliability of the thin film transistor, the thin film transistor obtained by Embodiment 1 is covered with the insulating layers (the insulating layer 4020 and the insulating layer 4021) functioning as a protective film or a planarizing insulating film. Note that the protective film is provided to prevent entry of impurities floating in the air, such as an organic substance, a metal substance, or moisture, and is preferably a dense film. The protective film may be formed by sputtering to be a single-layer film or a multi-layer film of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, and/or an aluminum nitride oxide film. Although this embodiment shows an example of forming the protective film by sputtering, there is no particular limitation on this method and a variety of methods such as a PCVD method may be employed. In part of the driver circuit, this protective film functions as the second gate insulating layer and a thin film transistor in which a back gate is provided over the second gate insulating layer is included.

In this embodiment, the insulating layer 4020 having a stacked structure is formed as the protective film. As a first layer of the insulating layer 4020, a silicon oxide film is formed by sputtering. The use of the silicon oxide film as the protective film has an effect of preventing a hillock of an aluminum film used for the source and drain electrode layers.

The insulating layer is also formed as a second layer of the protective film. In this embodiment, as a second layer of the insulating layer 4020, a silicon nitride film is formed by sputtering. The use of the silicon nitride film as the protective film can prevent ions such as sodium ions from entering a semiconductor region, thereby suppressing variations in electric characteristics of the TFT.

After the protective film is formed, the semiconductor layer may be annealed (at 300° C. to 400° C.). Further, after the protective film is formed, a back gate is formed.

The insulating layer 4021 is formed as the planarizing insulating film. For the insulating layer 4021, an organic material having heat resistance, such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy, can be used. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. Note that the insulating layer 4021 may be formed by stacking a plurality of insulating films formed of these materials.

Note that a siloxane-based resin is a resin formed from a siloxane material as a starting material and having the bond of Si—O—Si. As for the siloxane-based resin, an organic group (e.g., an alkyl group or an aryl group) or a fluoro group may be used as a substituent. In addition, the organic group may include a fluoro group.

There is no particular limitation on the method for forming the insulating layer 4021, and the insulating layer 4021 can be formed, depending on the material, by sputtering, SOG, spin coating, dipping, spray coating, droplet discharging (e.g., ink-jet, screen printing, or offset printing), doctor knife, roll coater, curtain coater, knife coater, or the like. In the case where the insulating layer 4021 is formed of a material solution, the semiconductor layer may be annealed (at 300° C. to 400° C.) at the same time of a baking step. The baking step of the insulating layer 4021 also functions as the annealing step of the semiconductor layer, whereby a semiconductor device can be manufactured efficiently.

The pixel electrode layer 4030 and the counter electrode layer 4031 can be made of a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter, referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.

A conductive composition containing a conductive high molecule (also referred to as a conductive polymer) can be used for the pixel electrode layer 4030 and the counter electrode layer 4031. The pixel electrode made of the conductive composition preferably has a sheet resistance of 10000 ohms per square or less and a light transmittance of 70% or more at a wavelength of 550 nm. Furthermore, the resistivity of the conductive high molecule contained in the conductive composition is preferably 0.1 Ω·cm or less.

As the conductive high molecule, a so-called π-electron conjugated conductive molecule can be used. For example, it is possible to use polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds of them.

In addition, a variety of signals and potentials are supplied to the signal line driver circuit 4003 that is formed separately, and the scan line driver circuit 4004 or the pixel portion 4002 from an FPC 4018.

In this embodiment, a connection terminal electrode 4015 is formed using the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013, and a terminal electrode 4016 is formed using the same conductive film as source and drain electrode layers of the thin film transistors 4010 and 4011.

The connection terminal electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

Note that FIGS. 21A1 and 21A2 illustrate an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

FIG. 22 illustrates an example of a liquid crystal display module which is formed as a semiconductor device by using a TFT substrate 2600.

FIG. 22 illustrates an example of a liquid crystal display module, in which the TFT substrate 2600 and a counter substrate 2601 are bonded to each other with a sealant 2602, and a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, a coloring layer 2605, and a polarizing plate 2606 are provided between the substrates to form a display region. The coloring layer 2605 is necessary to perform color display. In the case of the RGB system, respective coloring layers corresponding to colors of red, green, and blue are provided for respective pixels. The polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are provided outside the TFT substrate 2600 and the counter substrate 2601. A light source includes a cold cathode tube 2610 and a reflective plate 2611. A circuit board 2612 is connected to a wiring circuit portion 2608 of the TFT substrate 2600 through a flexible wiring board 2609 and includes an external circuit such as a control circuit or a power supply circuit. The polarizing plate and the liquid crystal layer may be stacked with a retardation plate interposed therebetween.

For the liquid crystal display module, a TN (twisted nematic) mode, an IPS (in-plane-switching) mode, an FFS (fringe field switching) mode, an MVA (multi-domain vertical alignment) mode, a PVA (patterned vertical alignment) mode, an ASM (axially symmetric aligned micro-cell) mode, an OCB (optical compensated birefringence) mode, an FLC (ferroelectric liquid crystal) mode, an AFLC (antiferroelectric liquid crystal) mode, or the like can be used.

Through the above-described steps, a liquid crystal display device can be manufactured as a semiconductor device at lower manufacturing cost.

This embodiment can be combined with the structure described in Embodiment 1, Embodiment 2, or Embodiment 3 as appropriate.

Embodiment 8

A semiconductor device according to one embodiment of the present invention can be applied to a variety of electronic appliances (including game machines). As the electronic appliances, for example, there are a television device (also referred to as a TV or a television receiver), a monitor for a computer or the like, a digital camera, a digital video camera, a digital photo frame, a cellular phone (also referred to as a mobile phone or a portable telephone device), a portable game machine, a portable information terminal, an audio reproducing device, and a large game machine such as a pachinko machine.

FIG. 23A illustrates an example of a portable information terminal device 9200. The portable information terminal device 9200 incorporates a computer and thus can process various types of data. An example of the portable information terminal device 9200 is a personal digital assistant (PDA).

The portable information terminal device 9200 has two housings, a housing 9201 and a housing 9203. The housing 9201 and the housing 9203 are joined with a joining portion 9207 such that the portable information terminal device 9200 can be foldable. A display portion 9202 is incorporated in the housing 9201, and the housing 9203 includes a keyboard 9205. Needless to say, the structure of the portable information terminal device 9200 is not limited to the above structure, and the structure may include at least a thin film transistor having a back-gate electrode, and additional accessory may be provided as appropriate. By forming a driver circuit and a pixel portion over the same substrate, a portable information terminal device including a thin film transistor having excellent electric characteristics can be provided at lower manufacturing cost.

FIG. 23B illustrates an example of a digital video camera 9500. The digital video camera 9500 includes a display portion 9503 incorporated in a housing 9501 and various operation portions. Note that there is no particular limitation on the structure of the digital video camera 9500, and the structure may include at least a thin film transistor having a back-gate electrode, and additional accessory may be provided as appropriate. By forming a driver circuit and a pixel portion over the same substrate, a digital video camera including a thin film transistor having excellent electric characteristics can be provided at lower manufacturing cost.

FIG. 23C illustrates an example of a cellular phone 9100. The cellular phone 9100 has two housings, a housing 9102 and a housing 9101. The housing 9102 and the housing 9101 are joined with a joining portion 9103 such that the cellular phone is foldable. A display portion 9104 is incorporated in the housing 9102, and the housing 9101 includes operation keys 9106. Note that there is no particular limitation on the structure of the cellular phone 9100, and the structure may include at least a thin film transistor having a back-gate electrode, and additional accessory may be provided as appropriate. By forming a driver circuit and a pixel portion over the same substrate, a cellular phone including a thin film transistor having excellent electric characteristics can be provided at lower manufacturing cost.

FIG. 23D illustrates an example of a portable computer 9400. The computer 9400 has two housings, a housing 9401 and a housing 9404. The housing 9401 and the housing 9404 are joined such that the computer can be open and closed. A display portion 9402 is incorporated in the housing 9401, and the housing 9404 includes a key board 9403. Note that there is no particular limitation on the structure of the computer 9400, and the structure may include at least a thin film transistor having a back-gate electrode, and additional accessory may be provided as appropriate. By forming a driver circuit and a pixel portion over the same substrate, a computer including a thin film transistor having excellent electric characteristics can be provided at lower manufacturing cost.

FIG. 24A illustrates an example of a television device 9600. A display portion 9603 is incorporated in a housing 9601 of the television device 9600. The display portion 9603 can display images. Here, the housing 9601 is supported on a stand 9605.

The television device 9600 can be operated by an operation switch of the housing 9601 or a separate remote controller 9610. The channel and volume can be controlled with operation keys 9609 of the remote controller 9610 and the images displayed in the display portion 9603 can be controlled. Moreover, the remote controller 9610 may have a display portion 9607 in which the information output from the remote controller 9610 is displayed.

Note that the television device 9600 is provided with a receiver, a modem, and the like. With the use of the receiver, general television broadcasting can be received. Moreover, when the display device is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) information communication can be performed.

FIG. 24B illustrates an example of a digital photo frame 9700. For example, a display portion 9703 is incorporated in a housing 9701 of the digital photo frame 9700. The display portion 9703 can display a variety of images, for example, display image data taken with a digital camera or the like, so that the digital photo frame can function in a manner similar to a general picture frame.

Note that the digital photo frame 9700 is provided with an operation portion, an external connection terminal (such as a USB terminal or a terminal which can be connected to a variety of cables including a USB cable), a storage medium inserting portion, and the like. These structures may be incorporated on the same plane as the display portion; however, they are preferably provided on the side surface or rear surface of the display portion because the design is improved. For example, a memory including image data taken with a digital camera is inserted into the storage medium inserting portion of the digital photo frame and the image data is imported. Then, the imported image data can be displayed in the display portion 9703.

The digital photo frame 9700 may send and receive information wirelessly. In this case, desired image data can be wirelessly imported into the digital photo frame 9700 and can be displayed therein.

FIG. 25A illustrates an example of a cellular phone 1000 which is different from the cellular phone of FIG. 23C. The cellular phone 1000 includes a housing 1001 in which a display portion 1002 is incorporated, and moreover includes an operation button 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like.

Information can be input to the cellular phone 1000 illustrated in FIG. 25A by touching the display portion 1002 with a finger or the like. Moreover, operation such as making a call or text messaging can be performed by touching the display portion 1002 with a finger or the like.

There are mainly three screen modes of the display portion 1002. The first mode is a display mode mainly for displaying an image. The second mode is an input mode mainly for inputting information such as text. The third mode is a display-and-input mode in which two modes of the display mode and the input mode are mixed.

For example, in the case of making a call or text messaging, the display portion 1002 is set to a text input mode where text input is mainly performed, and text input operation can be performed on a screen. In this case, it is preferable to display a keyboard or number buttons on almost the entire screen of the display portion 1002.

When a detection device including a sensor for detecting inclination, such as a gyroscope or an acceleration sensor, is provided inside the cellular phone 1000, display in the screen of the display portion 1002 can be automatically switched by judging the direction of the cellular phone 1000 (whether the cellular phone 1000 is placed horizontally or vertically for a landscape mode or a portrait mode).

Further, the screen modes are switched by touching the display portion 1002 or operating the operation button 1003 of the housing 1001. Alternatively, the screen modes can be switched depending on kinds of images displayed in the display portion 1002. For example, when a signal for an image displayed in the display portion is data of moving images, the screen mode is switched to the display mode. When the signal is text data, the screen mode is switched to the input mode.

Moreover, in the input mode, when input by touching the display portion 1002 is not performed within a specified period while a signal detected by an optical sensor in the display portion 1002 is detected, the screen mode may be controlled so as to be switched from the input mode to the display mode.

The display portion 1002 can also function as an image sensor. For example, an image of a palm print, a fingerprint, or the like is taken by touching the display portion 1002 with the palm or the finger, whereby personal authentication can be performed. Moreover, when a backlight which emits near-infrared light or a sensing light source which emits near-infrared light is provided in the display portion, a finger vein, a palm vein, or the like can be taken.

FIG. 25B also illustrates an example of a cellular phone. The cellular phone in FIG. 25B includes an a display device 9410 in which a display portion 9412 and an operation button 9413 are included in a housing 9411, and a communication device 9420 in which operation buttons 9422, an external input terminal 9423, a microphone 9424, a speaker 9405, and a light-emitting portion 9406 that emits light when a phone call is received are included in a housing 9421. The display device 9410 having a display function can be detached from or attached to the communication device 9420 having a telephone function in two directions as indicated by arrows. Thus, a minor axis of the display device 9410 can be attached to a minor axis of the communication device 9420, and a major axis of the display device 9410 can be attached to a major axis of the communication device 9420. In addition, when only the display function is required, the display device 9410 can be detached from the communication device 9420 so that the display device 9410 can be separately used. Images or input information can be transmitted or received between the communication device 9400 and the display device 9410 through wired communication or wireless communication. The communication device 9420 and the display device 9410 each have a rechargeable battery.

Embodiment 9

In this embodiment, an example of a display device including a thin film transistor having a structure in which a second oxide semiconductor layer (an n⁺ layer) is included between a source wiring (or a drain wiring) and a semiconductor layer is illustrated in FIG. 26. Note that in FIG. 26, the same parts as those in FIG. 1A are denoted with the same reference numerals.

A first thin film transistor 480 illustrated in FIG. 26 is a thin film transistor used for a driver circuit, and is an example in which an n⁺ layer 406 a is provided between the oxide semiconductor layer 405 and the first wiring 409 and an n⁺ layer 406 b is provided between the oxide semiconductor layer 405 and the second wiring 410. The first thin film transistor 480 includes the first gate electrode 401 below the oxide semiconductor layer 405 and the second gate electrode 470 above the oxide semiconductor layer 405.

Further, a second thin film transistor 481 is a thin film transistor used for a pixel portion, and is an example in which n⁺ layers 104 a and 104 b are provided between the oxide semiconductor layer 103 and the source and drain electrode layers 105 a and 105 b, respectively.

The n⁺ layers are oxide semiconductor layers with lower resistance than the oxide semiconductor layer 405 and the oxide semiconductor layer 103, and function as source regions and drain regions.

The n⁺ layer is formed by sputtering using In₂O₃, Ga₂O₃, and ZnO as a target including at a ratio of In₂O₃:Ga₂O₃:ZnO=1:1:1 under conditions in which the pressure is 0.4 Pa, power is 500 W, film formation temperature is a room temperature, and an argon gas is introduced at a flow rate of 40 sccm. Even when a target of In₂O₃, Ga₂O₃, and ZnO (In₂O₃:Ga₂O₃:ZnO=1:1:1) is intentionally used, an In—Ga—Zn—O-based non-single-crystal film containing crystal grains with sizes of 1 nm to 10 nm immediately after the film formation is formed in some cases. Note that when a ratio of components of the target, a film formation pressure (0.1 Pa to 2.0 Pa), power (250 W to 3000 W: 8 inchφ), temperature (room temperature to 100° C.), film formation conditions of reactive sputtering, and the like are adjusted as appropriate, existence of crystal grains and density of the crystal grains can be controlled, and the diameter of the crystal grains can also be controlled in a range of 1 nm to 10 nm A thickness of the second In—Ga—Zn—O-based non-single-crystal film is 5 nm to 20 nm. Needless to say, in the case where crystal grains are contained in the film, the size of the contained crystal grains does not exceed the film thickness. In this embodiment, the thickness of the second In—Ga—Zn—O-based non-single-crystal film is 5 nm.

The semiconductor device of this embodiment has a structure in which the n⁺ layers are included between the wiring and the semiconductor layer, and thus operates thermally stably as compared with the semiconductor device including the Schottky junction of Embodiment 1.

Further, a conductive film which is to be the source and drain electrode layers 105 a and 105 b and an oxide semiconductor film which is to be the n⁺ layers are stacked by a sputtering method without being exposed to the atmosphere, so that the source electrode layer and the drain electrode layer are not exposed, and thus dust can be prevented from being attached thereto during the manufacturing process.

This embodiment can be implemented in combination with any of the structures described in the other embodiments, as appropriate.

This application is based on Japanese Patent Application Ser. No. 2008-274650 filed with Japanese Patent Office on Oct. 24, 2008, the entire contents of which are hereby incorporated by reference. 

1. (canceled)
 2. A semiconductor device comprising: a transistor comprising: a first gate electrode on an insulating surface; an oxide semiconductor layer over the first gate electrode; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and a second gate electrode over the oxide semiconductor layer; and a terminal comprising: a first conductive layer on the insulating surface; a first insulating layer including an opening over the first conductive layer; a second conductive layer electrically connected to the first conductive layer through the opening; and a transparent conductive layer over the second conductive layer, wherein the first gate electrode and the first conductive layer are formed by patterning a first layer, wherein the source electrode, the drain electrode, and the second conductive layer are formed by patterning a second layer, and wherein the second gate electrode and the transparent conductive layer are formed by patterning a third layer.
 3. The semiconductor device according to claim 2, wherein the first layer comprises a material selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium.
 4. The semiconductor device according to claim 2, wherein the second layer comprises a material selected from aluminum, chromium, tantalum, titanium, molybdenum, and tungsten.
 5. The semiconductor device according to claim 2, wherein the transparent conductive layer is electrically connected to a flexible printed circuit.
 6. The semiconductor device according to claim 2, wherein the transparent conductive layer is over and in contact with the second conductive layer.
 7. The semiconductor device according to claim 2, wherein the transistor is included in a driver circuit.
 8. A semiconductor device comprising: a transistor comprising: a first gate electrode on an insulating surface; an oxide semiconductor layer over the first gate electrode, the oxide semiconductor layer comprising indium and zinc; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and a second gate electrode over the oxide semiconductor layer; and a terminal comprising: a first conductive layer on the insulating surface; a first insulating layer including an opening over the first conductive layer; a second conductive layer electrically connected to the first conductive layer through the opening; and a transparent conductive layer over the second conductive layer, the transparent conductive layer comprising indium and zinc, wherein the first gate electrode and the first conductive layer are formed by patterning a first layer, wherein the source electrode, the drain electrode, and the second conductive layer are formed by patterning a second layer, wherein the second gate electrode and the transparent conductive layer are formed by patterning a third layer, and wherein a width of the second gate electrode is larger than a width of the first gate electrode.
 9. The semiconductor device according to claim 8, wherein the first layer comprises a material selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium.
 10. The semiconductor device according to claim 8, wherein the second layer comprises a material selected from aluminum, chromium, tantalum, titanium, molybdenum, and tungsten.
 11. The semiconductor device according to claim 8, wherein the transparent conductive layer is electrically connected to a flexible printed circuit.
 12. The semiconductor device according to claim 8, wherein the transparent conductive layer is over and in contact with the second conductive layer.
 13. The semiconductor device according to claim 8, wherein the transistor is included in a driver circuit.
 14. A semiconductor device comprising: a first transistor comprising: a first gate electrode on an insulating surface; a first insulating layer over the first gate electrode; an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer comprising indium and zinc; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; a second insulating layer over the source electrode and the drain electrode; and a second gate electrode over the second insulating layer; a second transistor comprising: a gate electrode on the insulating surface; the first insulating layer over the gate electrode; an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer comprising indium and zinc; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; the second insulating layer over the oxide semiconductor layer; and a pixel electrode electrically connected to the source electrode or the drain electrode; and a terminal comprising: a first conductive layer on the insulating surface; the first insulating layer including an opening over the first conductive layer; a second conductive layer electrically connected to the first conductive layer through the opening; and a transparent conductive layer over the second conductive layer, the transparent conductive layer comprising indium and zinc, wherein the first gate electrode of the first transistor, the gate electrode of the second transistor, and the first conductive layer are formed by patterning a first layer, wherein the source electrode of the first transistor, the drain electrode of the first transistor, the source electrode of the second transistor, the drain electrode of the second transistor, and the second conductive layer are formed by patterning a second layer, and wherein the second gate electrode of the first transistor, the pixel electrode, and the transparent conductive layer are formed by patterning a third layer.
 15. The semiconductor device according to claim 14, wherein the first layer comprises a material selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium.
 16. The semiconductor device according to claim 14, wherein the second layer comprises a material selected from aluminum, chromium, tantalum, titanium, molybdenum, and tungsten.
 17. The semiconductor device according to claim 14, wherein the transparent conductive layer is electrically connected to a flexible printed circuit.
 18. The semiconductor device according to claim 14, wherein the transparent conductive layer is over and in contact with the second conductive layer.
 19. The semiconductor device according to claim 14, wherein the first transistor is included in a driver circuit and the second transistor is included in a pixel portion. 